TEST: Test and dEpendability of microelectronic integrated SysTems

Les travaux conduits dans l’équipe TEST ont pour objectif principal le développement de modèles, de méthodes et d’outils permettant d’assurer la qualité d’un dispositif microélectronique intégré après fabrication.

Nos contributions principales concernent l’impact des technologies récentes et émergentes sur la qualité des dispositifs et les coûts de mise en oeuvre avec en particulier les problématiques liées à la complexité d’intégration, à la variabilité des paramètres de fabrication et à la consommation croissante des circuits intégrés. Elles concernent également la prise en compte des contraintes spécifiques liées aux circuits sécurisés et à l’environnement d’utilisation (spatial et radiatif). Les technologies étudiées, et leur prise en compte dans un flot de conception pour la création de systèmes fiables et testables, englobent les technologies CMOS avancées, par exemple FDSOI/FinFET, ainsi que les technologies de rupture comme l’intégration 3D où les technologies émergentes de mémoires.

Les recherches menées aboutissent à la proposition de nouveaux modèles de fautes, au développement d’instruments de monitoring ou de nouvelles méthodes de conception en vue du test et à la proposition de nouvelles architectures matérielles intégrées au système afin de surveiller son fonctionnement tout au long de sa vie.

L’équipe TEST est la plus grande équipe académique au niveau international dont les thématiques de recherche sont intégralement dédiées aux problématiques de test et fiabilité des composants constituant un système intégré microélectronique. Ceci lui permet d’adresser les multiples facettes de cette thématique : digital, analogique, RF, mémoires, ...

Activités scientifiques

Les activités scientifiques de l’équipe TEST sont structurées autour de 4 axes de recherche adressant les problématiques de Fiabilité et de Test dans les domaines suivants :

• Axe 1 : Circuits digitaux, analogiques et RFs

• Axe 2 : Circuits sécurisés

• Axe 3 : Technologies et Paradigmes Emergents

• Axe 4 : Environnements Spatial et Radiatif

L’axe 1 regroupe les activités « coeurs de métier » de l’équipe et les axes 2, 3, et 4 sont liés aux travaux menés dans les thèmes transversaux du département Microélectronique avec la prise en compte de contraintes spécifiques liées aux circuits sécurisés, aux technologies et paradigmes émergents ainsi qu’aux environnements hostiles.

Axe 1 : Fiabilité et Test des Circuits Digitaux, Analogiques et RFs

Les systèmes sur puce ont vu leur surface augmenter d’un facteur 10 et leur consommation multiplier par 5 lors des dix dernières années. Chaque saut technologique ayant permis cette intégration a aussi ajouté de nouvelles contraintes faisant obstacle à la fiabilité du système. Par exemple, l’augmentation des variations PVT ou de la densité et de la nature des défauts, l’ajout de structures spécifiques pour le contrôle de la puissance consommée…

Il est donc nécessaire de développer des solutions de test et d’amélioration de la fiabilité afin de garantir le rendement de production (le plus élevé possible) et la durée de vie du système (la plus longue possible). De plus, l’intégration de blocs analogiques et RF pose de nombreux problèmes, principalement liés au fait que les méthodes de l’état de l’art utilisées pour tester ces blocs nécessitent l’utilisation de ressources de test spécifiques extrêmement coûteuses par rapport aux ressources numériques disponibles sur un équipement de test standard.

Axe 2 : Fiabilité, Test, Confiance et Sécurité des Circuits Intégrés

L’accroissement massif de l’utilisation de systèmes communicants a introduit la sécurité comme pivot de leur développement. De plus, comme la conception et la fabrication de ces systèmes sont devenues des opérations extrêmement complexes et géographiquement distribuées sur toute la planète, de nouvelles vulnérabilités de sécurité et de confiance sont apparues. Par conséquence, la totalité du flot de production du matériel est devenue elle-même sujette à des problèmes de sécurité et de confiance, qui incluent les attaques par canaux cachés, la rétro-ingénierie, le piratage des propriétés intellectuelles (IP), jusqu’à la modification mal intentionnée des circuits.

Axe 3 : Fiabilité et Test des technologies émergentes

La fin prévue de la course à la miniaturisation entraine aujourd’hui la communauté vers une démarche en rupture, usuellement intitulée « More than Moore ». La stratégie dans ce cadre consiste à explorer des solutions relevant du changement de matériaux, d’architectures, de méthodes ou de paradigmes de conception.

Axe 4 : Fiabilité et Test en environnements spatial et radiatif

Les composants électroniques peuvent être soumis à différentes sources de radiations en fonction du contexte applicatif que ce soient des environnements naturels comme l’espace et l’atmosphère ou des environnements artificiels tels que les accélérateurs de particules ou les réacteurs nucléaires.

Ces radiations peuvent entrainer des perturbations dans le fonctionnement des systèmes intégrés microélectroniques. De nombreuses applications sensibles ne peuvent tolérer un taux de défaillance important du fait de leur criticité. De part la complexité des effets induits par les radiations ionisantes, nos travaux dans ce domaine portent sur le développement de méthodes d'analyse et d'expérimentation. En plus des effets radiatifs, les effets de la température sont également pris en compte dans le cadre de cet axe de recherche.

Contrats de Recherche

TRUDEVICE :

Trustworthy Manufacturing and Utilization of Secure Devices

CLERECO :

Cross-Layer Early Reliability Evaluation for the Computing cOntinuum

MTCUBE :

Memory Test CUBEsat

TEEVA :

TEEVA - Trusted Execution Environment

Rayonnement

Les membres de l’équipe sont fortement impliqués dans les conférences ETS «European Test Symposium» (organisation en 2013, président de comité des programmes de 2015 à 2016, Publication Chair de 2015 à 2016 et membres du Steering Commitee), VTS « VLSI Test Symposium » (Publication Chair depuis 2012, General chair en 2013 et membre du comité des programmes) et DATE «Design Automation and Test in Europe» (Program Vice-Chair en 2016 et Program Chair en 2017, membre du comité exécutif depuis 2013).

Nous participons aussi très activement aux conférences et workshop internationaux relatifs à nos axes de recherche : IEEE Computer Society Annual Symposium on VLSI (Program Co-Chair en 2016 General co-chair en 2015 et Track Chair de 2015 à 2017 et Publication Chair en 2015), Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (General chair de 2013 à 2016 et Program Chair de 2013 à 2014), IEEE International Mixed-Signals Test Workshop (Chair du Steering Committe de 2013 à 2016, Program Chair en 2014). Des membres de l’équipe sont aussi impliqués dans les comités de lecture des revues majeures de notre domaine : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Computers, JETTA – Journal of Electronic Testing – Theory and Applications, IEEE Transactions on Very Large Scale Integration Systems, IEEE Transactions on Emerging Topics in Computing, JOLPE - Journal of Low Power Electronics, ACM Journal of Emerging Technologies in Computing Systems.

Nous participons aussi très activement à l’IEEE Computer Society European TTTC (Test Technology Technical Council) (Chair depuis 2014, Electronic Media chair depuis 2012).

Au niveau national, nous sommes fortement impliqués dans le GdR SoC-SiP/SoC2 (directeur adjoint, création et responsabilité du groupe de travail Sécurité des Systèmes Matériels, membres du comité de pilotage), dans le pré-GdR Sécurité Informatique (membre du bureau) et dans le GdR ERRATA (membre du bureau et organisation des journées thématiques RADSOL).

Membres

Permanents

Non permanents

Publications depuis 2014 - Evaluation 2019

Articles de revues internationales

2019

  1. Pre-flight qualification test procedure for nanosatellites using sounding rockets
    Leonardo Kessler Slongo, João Reis, Daniel Gaiki, Pedro Von Hohendorff Seger, Sara Vega Martinez, Bruno Vale Barbosa Eiterer, Tulio Gomes Pereira, Mario Baldini Neto, Mateus Dos Santos Frata, Juan Florez Mera, Kleber Paiva, Marcia Barbosa Henriques Mantelli, Luigi Dilillo, Eduardo Augusto Bezerra
    Acta Astronautica, Elsevier, 2019, 159, pp.564-577. ⟨10.1016/j.actaastro.2019.01.035⟩. ⟨lirmm-02008287⟩.
  2. Logic Locking: A Survey of Proposed Methods and Evaluation Metrics
    Sophie Dupuis, Marie-Lise Flottes
    Journal of Electronic Testing, Springer Verlag, In press, &#x27E8;10.1007/s10836-019-05800-4&#x27E9;. &#x27E8;lirmm-02128826&#x27E9;. <10.1007/s10836-019-05800-4>
  3. Low-Cost Digital Test Solution for Symbol Error Detection of RF ZigBee Transmitters
    Thibault Vayssade, Florence Azaïs, Laurent Latorre, Francois Lefèvre
    IEEE Transactions on Device and Materials Reliability, Institute of Electrical and Electronics Engineers, 2019, 19 (1), pp.16-24. &#x27E8;10.1109/TDMR.2019.2898769&#x27E9;. &#x27E8;lirmm-02077048&#x27E9;.
  4. Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption
    Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2019, 38 (3), pp.538-550. &#x27E8;10.1109/TCAD.2018.2818722&#x27E9;. &#x27E8;lirmm-01867245&#x27E9;.
  5. Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies
    Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Galliere, Michel Renovell
    Journal of Electronic Testing, Springer Verlag, 2019, 35 (1), pp.59-75. &#x27E8;10.1007/s10836-019-05776-1&#x27E9;. &#x27E8;lirmm-02075690&#x27E9;.
  6. Improvement of the Tolerated Raw Bit Error Rate in NAND Flash-based SSDs with Selective Refresh
    Emna Farjallah, Jean-Marc Armani, Valentin Gherman, Luigi Dilillo
    Microelectronics Reliability, Elsevier, In press. &#x27E8;lirmm-02008002&#x27E9;.
  7. Sensitivity to Laser Fault Injection: CMOS FD-SOI vs. CMOS bulk
    J.-M. Dutertre, Vincent Beroulle, Philippe Candelier, Stephan de Castro, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hely, Regis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre
    IEEE Transactions on Device and Materials Reliability, Institute of Electrical and Electronics Engineers, 2019, 19 (1), pp.6-15. &#x27E8;10.1109/TDMR.2018.2886463&#x27E9;. &#x27E8;hal-01971932&#x27E9;.
  8. Study of the impact of the LHC radiation environments on the Synergistic Displacement Damage and Ionizing Dose Effect on Electronic Components
    Rudy Ferraro, Salvatore Danzeca, Chiara Cangialosi, Ruben Garcia Alia, Francesco Cerutti, Andrea Tsinganis, Luigi Dilillo, Markus Brugger, Alessandro Masi
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, In press. &#x27E8;lirmm-02016480&#x27E9;.

2018

  1. Assessing Body Built-In Current Sensors for Detection of Multiple Transient Faults
    Raphael Andreoni Camponogara-Viera, Jean-Max Dutertre, Marie-Lise Flottes, Olivier Potin, Giorgio Di Natale, Bruno Rouzeyre, Rodrigo Possamai Bastos
    Microelectronics Reliability, Elsevier, 2018, 88-90 (29th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2018)), pp.128-134. &#x27E8;10.1016/j.microrel.2018.07.111&#x27E9;. &#x27E8;hal-01893676&#x27E9;.
  2. Single-Event Effects in the Peripheral Circuitry of a Commercial Ferroelectric Random Access Memory
    Alexandre Louis Bosser, Viyas Gupta, Arto Javanainen, Georgios Tsiligiannis, Stephen Lalumondiere, Dale Brewe, Véronique Ferlet-Cavrois, Helmut Puchner, Heikki Kettunen, Thierry Gil, Frédéric Wrobel, F. Saigné, Ari Virtanen, Luigi Dilillo
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2018, 65 (8), pp.1708-1714. &#x27E8;10.1109/TNS.2018.2797543&#x27E9;. &#x27E8;lirmm-02007922&#x27E9;.
  3. On-chip Generation of Sine-wave Summing Digital Signals: an Analytic Study Considering Implementation Constraints
    Stéphane David-Grignot, Achraf Lamlih, Mohamed Moez Belhaj, Vincent Kerzérho, Florence Azaïs, Fabien Soulier, Philippe Freitas, Tristan Rouyer, Sylvain Bonhommeau, Serge Bernard
    Journal of Electronic Testing, Springer Verlag, 2018, 34 (3), pp.281-290. &#x27E8;10.1007/s10836-018-5710-4&#x27E9;. &#x27E8;lirmm-01706621&#x27E9;.
  4. A Ring Oscillator-Based Identification Mechanism Immune to Aging and External Working Conditions
    Mario Barbareschi, Giorgio Di Natale, Lionel Torres, Antonino Mazzeo
    IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2018, 65 (2), pp.700-711. &#x27E8;10.1109/TCSI.2017.2727546&#x27E9;. &#x27E8;lirmm-01692481&#x27E9;.
  5. Protection against Hardware Trojans with Logic Testing: Proposed Solutions and Challenges Ahead
    Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    IEEE Design & Test, IEEE, 2018, 35 (2), pp.73-90. &#x27E8;10.1109/MDAT.2017.2766170&#x27E9;. &#x27E8;lirmm-01688166&#x27E9;.
  6. Scan-Chain Intra-Cell Aware Testing
    Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Matteo Sonza Reorda, Paolo Bernardi, Etienne Auvray
    IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2018, 6 (2), pp.278-287. &#x27E8;10.1109/TETC.2016.2624311&#x27E9;. &#x27E8;lirmm-01430859&#x27E9;.
  7. Towards a Dependable True Random Number Generator With Self-Repair Capabilities
    Honorio Martin, Giorgio Di Natale, Luis Entrena
    IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2018, 65 (1), pp.247-256. &#x27E8;10.1109/TCSI.2017.2711033&#x27E9;. &#x27E8;lirmm-01700736&#x27E9;.
  8. Test and Reliability in Approximate Computing
    Lorena Anghel, Mounir Benabdenbi, Alberto Bosio, Marcello Traiola, Elena Ioana Vatajelu
    Journal of Electronic Testing, Springer Verlag, 2018, 34 (4), pp.375-387. &#x27E8;10.1007/s10836-018-5734-9&#x27E9;. &#x27E8;hal-01961787&#x27E9;.
  9. SyRA: Early System Reliability Analysis for Cross-layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems
    Alessandro Vallero, Alessandro Savino, Athanasios Chatzidimitriou, Manolis Kaliorakis, Maha Kooli, Marc Riera Villanueva, Giorgio Di Natale, Alberto Bosio, Ramon Canal, Dimitris Gizopoulos, Stefano Di Carlo
    IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, In press, &#x27E8;10.1109/TC.2018.2887225&#x27E9;. &#x27E8;lirmm-01961657&#x27E9;. <10.1109/TC.2018.2887225>

2017

  1. A calculation method to estimate single event upset cross section
    Frédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Jérôme Boch, Frédéric Saigné
    Microelectronics Reliability, Elsevier, 2017, 76-77, pp.644-649. &#x27E8;10.1016/j.microrel.2017.07.056&#x27E9;. &#x27E8;hal-01636059&#x27E9;.
  2. Report on DATE 2017 in Lausanne
    David Atienza, Giorgio Di Natale
    IEEE Design & Test, IEEE, 2017, 34 (4), pp.76-77. &#x27E8;10.1109/MDAT.2017.2693266&#x27E9;. &#x27E8;lirmm-01700737&#x27E9;.
  3. Microprocessor Testing: Functional Meets Structural Test
    Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi
    Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2017, 26 (08), &#x27E8;10.1142/S0218126617400072&#x27E9;. &#x27E8;lirmm-01718578&#x27E9;. <10.1142/S0218126617400072>
  4. HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization
    Arnaud Virazel, Alejandro Nocua, Alberto Bosio, Patrick Girard, Cyril Chevalier
    Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2017, 26 (8), pp.#1740004. &#x27E8;10.1142/S0218126617400047&#x27E9;. &#x27E8;lirmm-01718575&#x27E9;.
  5. Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies
    Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel Renovell
    Journal of Electronic Testing, Springer Verlag, 2017, 33 (4), pp.515-527. &#x27E8;10.1007/s10836-017-5674-9&#x27E9;. &#x27E8;hal-01709587&#x27E9;.
  6. Heavy Ion Induced Degradation in SiC Schottky Diodes: Incident Angle and Energy Deposition Dependence
    Arto Javanainen, Marek Turowski, Kenneth Galloway, Christopher Nicklaw, Véronique Ferlet-Cavrois, Alexandre Bosser, Jean-Marie Lauenstein, Michele Muschitiello, Francesco Pintacuda, Robert Reed, Ronald Schrimpf, Robert Weller, Ari Virtanen
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2017, 64 (8), pp.2031-2037. &#x27E8;10.1109/TNS.2017.2717045&#x27E9;. &#x27E8;lirmm-02021535&#x27E9;.
  7. Computing reliability: On the differences between software testing and software fault injection techniques
    Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio, Pascal Benoit, Lionel Torres
    Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2017, 50, pp.102-112. &#x27E8;10.1016/j.micpro.2017.02.007&#x27E9;. &#x27E8;lirmm-01693156&#x27E9;.
  8. Influence of Body-Biasing, Supply Voltage, and Temperature on the Detection of Resistive Short Defects in FDSOI Technology
    Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel Renovell
    IEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers, 2017, 16 (3), pp.417-430. &#x27E8;10.1109/TNANO.2017.2664895&#x27E9;. &#x27E8;hal-01709588&#x27E9;.
  9. Design of a radiation tolerant system for total ionizing dose monitoring using floating gate and RadFET dosimeters
    Rudy Ferraro, Salvatore Danzeca, Matteo Brucoli, Alessandro Masi, Markus Brugger, Luigi Dilillo
    Journal of Instrumentation, IOP Publishing, 2017, 12 (4), pp.#C04007. &#x27E8;http://iopscience.iop.org/article/10.1088/1748-0221/12/04/C04007&#x27E9;. &#x27E8;10.1088/1748-0221/12/04/C04007&#x27E9;. &#x27E8;lirmm-01513884&#x27E9;.
  10. A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits
    Arnaud Virazel, Imran Wali, Bastien Deveautour, Alberto Bosio, Patrick Girard, M. Sonza Reorda
    Journal of Electronic Testing, Springer Verlag, 2017, 33 (1), pp.25-36. &#x27E8;10.1007/s10836-017-5640-6&#x27E9;. &#x27E8;lirmm-01718568&#x27E9;.
  11. A Cross-Level Power Estimation Technique to Improve IP Power Models Quality
    Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
    Journal of Low Power Electronics, American Scientific Publishers, 2017, 13 (1), pp.10-28. &#x27E8;10.1166/jolpe.2017.1472&#x27E9;. &#x27E8;lirmm-01433322&#x27E9;.

2016

  1. Soft errors in commercial off-the-shelf static random access memories
    Luigi Dilillo, Georgios Tsiligiannis, Viyas Gupta, Alexandre Louis Bosser, Frédéric Saigné, Frédéric Wrobel
    Semiconductor Science and Technology, IOP Publishing, 2016, Special Issue on Radiation Effects in Semiconductor Devices, 32 (1), &#x27E8;http://iopscience.iop.org/article/10.1088/1361-6641/32/1/013006/meta&#x27E9;. &#x27E8;10.1088/1361-6641/32/1/013006&#x27E9;. &#x27E8;lirmm-01434747&#x27E9;. <10.1088/1361-6641/32/1/013006>
  2. Frontside Versus Backside Laser Injection: A Comparative Study
    Stephan de Castro, Jean-Max Dutertre, Bruno Rouzeyre, Giorgio Di Natale, Marie-Lise Flottes
    ACM Journal on Emerging Technologies in Computing Systems, Association for Computing Machinery, 2016, Special Issue on Secure and Trustworthy Computing, 13 (1), pp.Art 7. &#x27E8;10.1145/2845999&#x27E9;. &#x27E8;lirmm-01444121&#x27E9;.
  3. An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization
    Kapil Juneja, Darayus Adil Patel, Rajesh Kumar Immadi, Balwant Singh, Sylvie Naudet, Pankaj Agarwal, Arnaud Virazel, Patrick Girard
    Journal of Electronic Testing, Springer Verlag, 2016, 32 (6), pp.721-733. &#x27E8;10.1007/s10836-016-5621-1&#x27E9;. &#x27E8;lirmm-01446887&#x27E9;.
  4. Ring oscillators analysis for security purposes in Spartan-6 FPGAs
    Mario Barbareschi, Giorgio Di Natale, Florent Bruguier, Pascal Benoit, Lionel Torres
    Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2016, 47 (Part A), pp.3-10. &#x27E8;10.1016/j.micpro.2016.06.005&#x27E9;. &#x27E8;lirmm-01421001&#x27E9;.
  5. The Power Law Shape of Heavy Ions Experimental Cross Section
    Frédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Eric Lorfèvre, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2016, 64 (1), pp.427-433. &#x27E8;10.1109/TNS.2016.2608004&#x27E9;. &#x27E8;lirmm-01382480&#x27E9;.
  6. Methodologies for the Statistical Analysis of Memory Response to Radiation
    Alexandre Louis Bosser, Viyas Gupta, Georgios Tsiligiannis, Christopher Frost, Ali Mohammad Zadeh, Jukka Jaatinen, Arto Javanainen, Helmut Puchner, Frédéric Saigné, Ari Virtanen, Frédéric Wrobel, Luigi Dilillo
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2016, 63 (4), pp.2122-2128. &#x27E8;10.1109/TNS.2016.2527781&#x27E9;. &#x27E8;lirmm-01382508&#x27E9;.
  7. Proton-Induced Single-Event Degradation in SDRAMs
    Axel Rodriguez, Frédéric Wrobel, Anne Samaras, Francoise Bezerra, Benjamin Vandevelde, Robert Ecoffet, Antoine Touboul, Christian Chatry, Luigi Dilillo, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2016, 63 (4), pp.2115-2121. &#x27E8;10.1109/TNS.2016.2551733&#x27E9;. &#x27E8;lirmm-01382563&#x27E9;.
  8. Heavy-Ion Radiation Impact on a 4 Mb FRAM Under Different Test Modes and Conditions
    Viyas Gupta, Alexandre Louis Bosser, Georgios Tsiligiannis, Ali Mohammad Zadeh, Arto Javanainen, Ari Virtanen, Helmut Puchner, Frédéric Saigné, Frédéric Wrobel, Luigi Dilillo
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2016, 63 (4), pp.2010-2015. &#x27E8;10.1109/TNS.2016.2559943&#x27E9;. &#x27E8;lirmm-01382552&#x27E9;.
  9. A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores
    Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda
    Journal of Electronic Testing, Springer Verlag, 2016, 32 (2), pp.147-161. &#x27E8;10.1007/s10836-016-5578-0&#x27E9;. &#x27E8;lirmm-01354746&#x27E9;.
  10. SSB Phase Noise Evaluation of Analog/IF Signals on Standard Digital ATE
    Florence Azaïs, Stéphane David-Grignot, Laurent Latorre, François Lefevre
    Journal of Electronic Testing, Springer Verlag, 2016, 32 (1), pp.69-82. &#x27E8;10.1007/s10836-015-5556-y&#x27E9;. &#x27E8;lirmm-01347312&#x27E9;.
  11. Introduction to Special Issue on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE)
    Lilian Bossuet, Giorgio Di Natale, Paris Kitsos
    Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2016, 47 (A), pp.1-2. &#x27E8;lirmm-01499334&#x27E9;.
  12. STT-MRAM-Based PUF Architecture exploiting Magnetic Tunnel Junction Fabrication-Induced Variability
    Ioana Vatajelu, Giorgio Di Natale, Mario Barbareschi, Lionel Torres, Marco Indaco, Paolo Prinetto
    ACM Journal on Emerging Technologies in Computing Systems, Association for Computing Machinery, 2016, 13 (1), &#x27E8;10.1145/2790302&#x27E9;. &#x27E8;lirmm-01234046&#x27E9;. <10.1145/2790302>
  13. Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits
    Florence Azaïs, Stéphane David-Grignot, Laurent Latorre, François Lefevre
    Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2016, 25 (3), pp.#1640014. &#x27E8;10.1142/S0218126616400144&#x27E9;. &#x27E8;lirmm-01233013&#x27E9;.
  14. Design for Test and Diagnosis of Power Switches
    Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Philippe Debaud, Stephane Guilhot
    Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2016, 25 (3), pp.1640013. &#x27E8;10.1142/S0218126616400132&#x27E9;. &#x27E8;lirmm-01272986&#x27E9;.

2015

  1. Investigation on MCU Clustering Methodologies for Cross-Section Estimation of RAMs
    Alexandre Louis Bosser, Viyas Gupta, Georgios Tsiligiannis, Arto Javanainen, Heikki Kettunen, Helmut Puchner, Frédéric Saigné, Ari Virtanen, Frédéric Wrobel, Luigi Dilillo
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2015, 62 (6), pp.2620-2626. &#x27E8;http://ieeexplore.ieee.org/Xplore/home.jsp&#x27E9;. &#x27E8;10.1109/TNS.2015.2496874&#x27E9;. &#x27E8;lirmm-01254157&#x27E9;.
  2. SEE on Different Layers of Stacked-SRAMs
    Viyas Gupta, Alexandre Louis Bosser, Georgios Tsiligiannis, Mathias Rousselet, Ali Mohammadzadeh, Arto Javanainen, Ari Virtanen, Helmut Puchner, Frédéric Saigné, Frédéric Wrobel, Luigi Dilillo
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2015, 62 (6), pp.2673-2678. &#x27E8;10.1109/TNS.2015.2496725&#x27E9;. &#x27E8;lirmm-01254148&#x27E9;.
  3. Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies
    Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, Michel Renovell
    Microelectronics Journal, Elsevier, 2015, 46 (11), pp.1091-1102. &#x27E8;10.1016/j.mejo.2015.09.014&#x27E9;. &#x27E8;lirmm-01232890&#x27E9;.
  4. Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview
    Alessandro Vallero, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Maha Kooli, Savino Alessandro, Politano Gianfranco, Alberto Bosio, Giorgio Di Natale, Dimitris Gizopoulos, Stefano Di Carlo
    Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2015, 39 (8), pp.1204-1214. &#x27E8;10.1016/j.micpro.2015.06.003&#x27E9;. &#x27E8;lirmm-01297595&#x27E9;.
  5. Phase Noise Testing of Analog/IF Signals Using Digital ATE: A New Post-Processing Algorithm for Extended Measurement Range
    Stéphane David-Grignot, Florence Azaïs, Laurent Latorre, François Lefevre
    Journal of Electronic Testing, Springer Verlag, 2015, 31 (5-6), pp.443-459. &#x27E8;10.1007/s10836-015-5548-y&#x27E9;. &#x27E8;lirmm-01233017&#x27E9;.

2014

  1. Heavy Ion SEU Cross Section Calculation Based on Proton Experimental Data, and Vice Versa
    Frédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Robert Ecoffet, Eric Lorfèvre, Francoise Bezerra, Markus Brugger, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (6), pp.3564-3571. &#x27E8;http://ieeexplore.ieee.org/Xplore/home.jsp&#x27E9;. &#x27E8;10.1109/TNS.2014.2368613&#x27E9;. &#x27E8;lirmm-01234461&#x27E9;.
  2. Use of CCD to Detect Terrestrial Cosmic Rays at Ground Level: Altitude vs. Underground Experiments, Modeling and Numerical Monte Carlo Simulation
    Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Philippe Cocquerez, Jean-Luc Autran, Antonio Litterio, Frédéric Wrobel, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (6), pp.3380-3388. &#x27E8;http://ieeexplore.ieee.org/Xplore/home.jsp&#x27E9;. &#x27E8;10.1109/TNS.2014.2365038&#x27E9;. &#x27E8;lirmm-01234455&#x27E9;.
  3. Dynamic Compact Model of Self-Referenced Magnetic Tunnel Junction
    João Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Jérémy Alvarez-Hérault, Ken Mackay
    IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2014, 61 (11), pp.3877-3882. &#x27E8;10.1109/TED.2014.2355418&#x27E9;. &#x27E8;lirmm-01272978&#x27E9;.
  4. Dynamic Test Methods for COTS SRAMs
    Georgios Tsiligiannis, Luigi Dilillo, Viyas Gupta, Alberto Bosio, Patrick Girard, Arnaud Virazel, Helmut Puchner, Alexandre Louis Bosser, Arto Javanainen, Ari Virtanen, Christopher Frost, Frédéric Wrobel, Laurent Dusseau, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (6), pp.3095-3102. &#x27E8;http://ieeexplore.ieee.org/Xplore/home.jsp&#x27E9;. &#x27E8;10.1109/TNS.2014.2363123&#x27E9;. &#x27E8;lirmm-01234463&#x27E9;.
  5. Testing Methods for PUF-Based Secure Key Storage Circuits
    Mafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di Natale
    Journal of Electronic Testing, Springer Verlag, 2014, 30 (5), pp.581-594. &#x27E8;10.1007/s10836-014-5471-7&#x27E9;. &#x27E8;lirmm-01234059&#x27E9;.
  6. Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS
    Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Alexandre Sarafianos
    Microelectronics Reliability, Elsevier, 2014, 54 (9-10), pp.2289-2294. &#x27E8;10.1016/j.microrel.2014.07.151&#x27E9;. &#x27E8;emse-01094805&#x27E9;.
  7. On the Test and Mitigation of Malfunctions in Low-Power SRAMs
    Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Nabil Badereddine
    Journal of Electronic Testing, Springer Verlag, 2014, 30 (5), pp.611-627. &#x27E8;http://link.springer.com/article/10.1007%2Fs10836-014-5479-z&#x27E9;. &#x27E8;10.1007/s10836-014-5479-z&#x27E9;. &#x27E8;lirmm-01238443&#x27E9;.
  8. Testing for Gate Oxide Short Defects using the Detectability Interval Paradigm
    Jean-Marc Galliere, Florence Azaïs, Mariane Comte, Michel Renovell
    Information Technology, Oldenbourg Verlag, 2014, 56 (4), pp.173-181. &#x27E8;http://www.degruyter.com/view/j/itit&#x27E9;. &#x27E8;10.1515/itit-2013-1040&#x27E9;. &#x27E8;hal-01167054&#x27E9;.
  9. Gate Voltage Contribution to Neutron-Induced SEB of Trench Gate Fieldstop IGBT
    Lionel Foro, Antoine Touboul, Alain Michez, Frédéric Wrobel, Paolo Rech, Luigi Dilillo, Christopher Frost, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (4), pp.1739-1746. &#x27E8;http://ieeexplore.ieee.org/Xplore/home.jsp&#x27E9;. &#x27E8;10.1109/TNS.2014.2332813&#x27E9;. &#x27E8;lirmm-01237646&#x27E9;.
  10. Evaluating a Radiation Monitor for Mixed-Field Environments based on SRAM Technology
    Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, Frédéric Wrobel, Frédéric Saigné
    Journal of Instrumentation, IOP Publishing, 2014, 9 (5), pp.#C05052. &#x27E8;10.1088/1748-0221/9/05/C05052&#x27E9;. &#x27E8;lirmm-01234448&#x27E9;.
  11. Multiple Cell Upset Classification in Commercial SRAMs
    Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Helmut Puchner, Christopher Frost, Frédéric Wrobel, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (4), pp.1747-1754. &#x27E8;http://ieeexplore.ieee.org/Xplore/home.jsp&#x27E9;. &#x27E8;10.1109/TNS.2014.2313742&#x27E9;. &#x27E8;lirmm-01234446&#x27E9;.
  12. On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis
    Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    Information Security Journal: A Global Perspective, Taylor & Francis, 2014, Trustworthy Manufacturing and Utilization of Secure Devices, 22 (5-6), pp.226-236. &#x27E8;10.1080/19393555.2014.891277&#x27E9;. &#x27E8;lirmm-00991362&#x27E9;.
  13. Multi-Level Ionizing-Induced Transient Fault Simulator
    Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    Information Security Journal: A Global Perspective, Taylor & Francis, 2014, 22 (5-6), pp.251-264. &#x27E8;http://www.tandfonline.com/doi/abs/10.1080/19393555.2014.891280#.VEEP7tTLc4l&#x27E9;. &#x27E8;10.1080/19393555.2014.891280&#x27E9;. &#x27E8;lirmm-01075393&#x27E9;.
  14. TRUDEVICE: A COST Action on "Trustworthy Manufacturing and Utilization of Secure Devices" (Editorial)
    Giorgio Di Natale
    Information Security Journal: A Global Perspective, Taylor & Francis, 2014, 22 (5-6), pp.205-207. &#x27E8;http://www.tandfonline.com/doi/abs/10.1080/19393555.2014.891283#.VEEVOdTLc4k&#x27E9;. &#x27E8;10.1080/19393555.2014.891283&#x27E9;. &#x27E8;lirmm-01075402&#x27E9;.
  15. Thwarting Scan-Based Attacks on Secure-ICs with On-Chip Comparison
    Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (4), pp.947-951. &#x27E8;10.1109/TVLSI.2013.2257903&#x27E9;. &#x27E8;lirmm-00841650&#x27E9;.
  16. Determining Realistic Parameters for the Double Exponential Law that Models Transient Current Pulses
    Frédéric Wrobel, Luigi Dilillo, Antoine Touboul, Vincent Pouget, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (4), pp.1813-1818. &#x27E8;http://ieeexplore.ieee.org/Xplore/home.jsp&#x27E9;. &#x27E8;10.1109/TNS.2014.2299762&#x27E9;. &#x27E8;lirmm-01234429&#x27E9;.
  17. Enhancing Confidence in Indirect Analog/RF Testing against the Lack of Correlation between Regular Parameters and Indirect Measurements
    Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, Michel Renovell
    Microelectronics Journal, Elsevier, 2014, 45 (3), pp.336-344. &#x27E8;10.1016/j.mejo.2013.12.006&#x27E9;. &#x27E8;lirmm-00936443&#x27E9;.
  18. An SRAM Based Monitor for Mixed-Field Radiation Environments
    Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, Frédéric Wrobel, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (4), pp.1663-1670. &#x27E8;http://ieeexplore.ieee.org/Xplore/home.jsp&#x27E9;. &#x27E8;10.1109/TNS.2014.2299733&#x27E9;. &#x27E8;lirmm-01234441&#x27E9;.
  19. Study of Low-Cost Electrical Test Strategies for Post-Silicon Yield Improvement of MEMS Convective Accelerometers
    Ahmed Rekik, Florence Azaïs, Frédérick Mailly, Pascal Nouet
    Journal of Electronic Testing, Springer Verlag, 2014, 30 (1), pp.87-100. &#x27E8;10.1007/s10836-013-5423-7&#x27E9;. &#x27E8;lirmm-00984275&#x27E9;.
  20. Test versus Security: Past and Present
    Jean Da Rolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
    IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2014, 2 (1), pp.50-62. &#x27E8;http://www.computer.org/csdl/trans/ec/preprint/06733305-abs.html&#x27E9;. &#x27E8;10.1109/TETC.2014.2304492&#x27E9;. &#x27E8;lirmm-00989627&#x27E9;.
  21. Intra-Cell Defects Diagnosis
    Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray
    Journal of Electronic Testing, Springer Verlag, 2014, 30 (5), pp.541-555. &#x27E8;10.1007/s10836-014-5481-5&#x27E9;. &#x27E8;lirmm-01272964&#x27E9;.
  22. A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems
    Ahn Duc Tran, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Hans-Joachim Wunderlich
    Journal of Electronic Testing, Springer Verlag, 2014, 30 (4), pp.401-413. &#x27E8;10.1007/s10836-014-5459-3&#x27E9;. &#x27E8;lirmm-01272958&#x27E9;.
  23. A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs
    João Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Jérémy Alvarez-Hérault, Ken Mackay
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (11), pp.2326-2335. &#x27E8;10.1109/TVLSI.2013.2294080&#x27E9;. &#x27E8;lirmm-01248578&#x27E9;.
  24. Globally Constrained Locally Optimized 3-D Power Delivery Networks
    Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (10), pp.2131-2144. &#x27E8;10.1109/TVLSI.2013.2283800&#x27E9;. &#x27E8;lirmm-01255754&#x27E9;.

Communications internationales

2019

  1. Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router
    Douglas Rossi de Melo, Cesar Zeferino, Luigi Dilillo, Eduardo Augusto Bezerra
    LATS: Latin-American Test Symposium, Mar 2019, Santiago, Chile. &#x27E8;lirmm-02008414&#x27E9;.
  2. A Fault-Tolerant Reconfigurable Platform for Communication Modules of Satellites
    Cézar Rigo, Lucas Matana Luza, Elder Dominghini Tramontin, Victor Martins, Sara Vega Martinez, Leonardo Kessler Slongo, Laio Oriel Seman, Luigi Dilillo, Fabian Luis Vargas, Eduardo Augusto Bezerra
    LATS: Latin-American Test Symposium, Mar 2019, Santiago, Chile. &#x27E8;lirmm-02008436&#x27E9;. <http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/>

2018

  1. Enabling deep-space CubeSat missions through state-of-the-art radiation-hardened technologies
    Lucas Matana Luza, Cézar Rigo, Elder Dominghini Tramontin, Victor Martins, Sara Vega Martinez, Leonardo Kessler Slongo, Laio Oriel Seman, Luigi Dilillo, Eduardo Augusto Bezerra
    IAA-LACW: Latin American CubeSat Workshop, Dec 2018, Ubatuba, Brazil. &#x27E8;lirmm-02008460&#x27E9;. <http://innalogics.com/iaalacw.org/iaalacw/>
  2. Implementation of fault tolerance techniques for integrated network interfaces
    Douglas Rossi de Melo, Cesar Zeferino, Luigi Dilillo, Eduardo Augusto Bezerra
    IAA-LACW: Latin American CubeSat Workshop, Dec 2018, Ubatuba, Brazil. &#x27E8;lirmm-02008453&#x27E9;.
  3. An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs
    Tien-Phu Ho, Eric Faehn, Arnaud Virazel, Alberto Bosio, Patrick Girard
    ITC: International Test Conference, Oct 2018, Phoenix, United States. pp.1-8, &#x27E8;10.1109/TEST.2018.8624799&#x27E9;. &#x27E8;lirmm-02099874&#x27E9;.
  4. Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits
    Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbarcschi, Alberto Bosio
    DFT: Defect and Fault Tolerance, Oct 2018, Chicago, United States. pp.1-6, &#x27E8;10.1109/DFT.2018.8602939&#x27E9;. &#x27E8;lirmm-02099895&#x27E9;.
  5. Study of the Impact of the LHC Radiation Environments on the Synergistic Displacement Damage and Ionizing Dose Effect on Electronic Components
    Rudy Ferraro, Salvatore Danzeca, Luigi Dilillo, Chiara Cangialosi, Ruben Garcia Alia, F. Cerutti, A. Tsinganis, A. Masi, Markus Brugger
    RADECS: Radiation Effects on Components and Systems, Sep 2018, Göteborg, Sweden. &#x27E8;lirmm-02008384&#x27E9;. <http://www.radecs2018.org>
  6. Approximate TMR Based on Successive Approximation to Protect Against Multiple Bit Upset in Microprocessors
    Gennaro Rodrigues, Fernanda Lima Kastensmidt, Vincent Pouget, Alberto Bosio
    RADECS: Radiation Effects on Components and Systems, Sep 2018, Goteborg, Sweden. &#x27E8;hal-02088922&#x27E9;.
  7. SEE Flux and Spectral Hardness Calibration of Neutron Spallation and Mixed Field Facilities
    Matteo Cecchetto, Ruben Garcia Alia, Pablo Fernandez-Martinez, Rudy Ferraro, Salvatore Danzeca, Frédéric Wrobel, Carlo Cazzaniga, Christopher Frost
    RADECS: Radiation Effects on Components and Systems, Sep 2018, Goteborg, Sweden. &#x27E8;hal-02086446&#x27E9;. <http://www.radecs2018.org>
  8. Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model
    Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Stephan de Castro, Faber Louis-Barthelemy, Marie-Lise Flottes, Philippe Gendrier, David Hely, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre
    FDTC: Fault Diagnosis and Tolerance in Cryptography, Sep 2018, Amsterdam, Netherlands. &#x27E8;10.1109/FDTC.2018.00009&#x27E9;. &#x27E8;emse-01856008&#x27E9;. <10.1109/FDTC.2018.00009>
  9. Exploiting Phase Information in Thermal Scans for Stealthy Trojan Detection
    Maxime Cozzi, Jean-Marc Galliere, Philippe Maurine
    DSD: Digital System Design, Aug 2018, Prague, Slovakia. pp.573-576, &#x27E8;10.1109/DSD.2018.00100&#x27E9;. &#x27E8;lirmm-01872499&#x27E9;.
  10. The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks
    Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hely, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre
    IOLTS: International On-Line Testing Symposium, Jul 2018, Platja d’Aro, Spain. pp.214-219, &#x27E8;10.1109/IOLTS.2018.8474230&#x27E9;. &#x27E8;emse-01856000&#x27E9;.
  11. Combined analysis of supply voltage and body-bias voltage for energy management
    Rida Kheirallah, Jean-Marc Galliere, Nadine Azemard, Gilles Ducharme
    PATMOS: Power and Timing Modeling, Optimization and Simulation, Jul 2018, Platja d’Aro, Spain. pp.88-91, &#x27E8;10.1109/PATMOS.2018.8464159&#x27E9;. &#x27E8;lirmm-01867809&#x27E9;.
  12. Encryption of test data: which cipher is better?
    Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno Rouzeyre
    PRIME: PhD Research in Microelectronics and Electronics, Jul 2018, Prague, Czech Republic. pp.85-88, &#x27E8;10.1109/PRIME.2018.8430366&#x27E9;. &#x27E8;lirmm-01867249&#x27E9;.
  13. A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation
    Honorio Martin, Luis Entrena, Sophie Dupuis, Giorgio Di Natale
    IOLTS: International Symposium on On-Line Testing And Robust System Design, Jul 2018, Platja d'Aro, Spain. pp.41-42, &#x27E8;10.1109/IOLTS.2018.8474077&#x27E9;. &#x27E8;lirmm-02095736&#x27E9;.
  14. Low-cost functional test of a 2.4 GHz OQPSK transmitter using standard digital ATE
    Thibault Vayssade, Florence Azaïs, Laurent Latorre, Francois Lefèvre
    IOLTS: International On-Line Testing Symposium, Jul 2018, Platja d'Aro, Spain. pp.17-22, &#x27E8;10.1109/IOLTS.2018.8474229&#x27E9;. &#x27E8;lirmm-01997910&#x27E9;.
  15. A new secure stream cipher for scan chain encryption
    Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno Rouzeyre
    IVSW: International Verification and Security Workshop, Jul 2018, Platja d’Aro, Spain. &#x27E8;lirmm-01867256&#x27E9;. <http://tima.univ-grenoble-alpes.fr/conferences/ivsw/ivsw18/>
  16. Performances VS Reliability: how to exploit Approximate Computing for Safety-Critical applications
    Gennaro Rodrigues, Fernanda Kastensmidt, Vincent Pouget, Alberto Bosio
    IOLTS: International On-Line Testing Symposium, Jul 2018, Platja d'Aro, Spain. pp.291-294, &#x27E8;10.1109/IOLTS.2018.8474122&#x27E9;. &#x27E8;hal-02095642&#x27E9;.
  17. SECCS: SECure Context Saving for IoT Devices
    Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
    Colloque GDR SoC2, Jun 2018, Paris, France. &#x27E8;hal-02042659&#x27E9;.
  18. Distributed Optical Fiber Radiation Sensing at CERN
    Gaetano Li Vecchi, Markus Brugger, Salvatore Danzeca, Diego Di Francesca, Rudy Ferraro, Sylvain Girard, Yacine Kadi, Oliver Stein
    9th International Particle Accelerator Conference, Apr 2018, Vancouver, Canada. pp.WEPAF083, &#x27E8;10.18429/JACoW-IPAC2018-WEPAF083&#x27E9;. &#x27E8;hal-01867520&#x27E9;.
  19. Thermal Scans for Detecting Hardware Trojans
    Maxime Cozzi, Philippe Maurine, Jean-Marc Galliere
    COSADE: Constructive Side-Channel Analysis and Secure Design, Apr 2018, Singapour, Singapore. pp.117-132, &#x27E8;10.1007/978-3-319-89641-0_7&#x27E9;. &#x27E8;lirmm-01823444&#x27E9;.
  20. SECCS: SECure Context Saving for IoT Devices
    Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2018, Taormina, Italy. &#x27E8;hal-01740173&#x27E9;. <www.lirmm.fr/DTIS18/>
  21. Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells
    Emna Farjallah, Valentin Gherman, Jean-Marc Armani, Luigi Dilillo
    DTIS: Design & Technology of Integrated Systems In Nanoscale Era, Apr 2018, Taormina, Italy. pp.1-5, &#x27E8;10.1109/DTIS.2018.8368578&#x27E9;. &#x27E8;lirmm-02008214&#x27E9;.
  22. Does stream cipher-based scan chains encryption really prevent scan attacks?
    Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    TRUDEVICE Workshop, Mar 2018, Dresden, Germany. &#x27E8;lirmm-01867286&#x27E9;. <https://www.date-conference.com/date18/conference/workshop-w05>
  23. Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies
    Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Galliere, Michel Renovell
    LATS: Latin-American Test Symposium, Mar 2018, Sao Paulo, Brazil. pp.1-5, &#x27E8;10.1109/LATW.2018.8349696&#x27E9;. &#x27E8;lirmm-02064921&#x27E9;.
  24. Exploring the inherent fault tolerance of successive approximation algorithms under laser fault injection
    Gennaro Rodrigues, Fernanda Kastensmidt, Vincent Pouget, Alberto Bosio
    LATS: Latin-American Test Symposium, Mar 2018, Sao Paulo, Brazil. pp.1-6, &#x27E8;10.1109/LATW.2018.8349675&#x27E9;. &#x27E8;hal-02095644&#x27E9;.

2017

  1. An Advanced Diagnosis Flow for SRAMs
    Arnaud Virazel, Tien-Phu Ho, Alberto Bosio
    ISTFA: International Symposium for Testing and Failure Analysis, Nov 2017, Pasadena, United States. &#x27E8;lirmm-01718596&#x27E9;. <https://www.asminternational.org/web/istfa-2017>
  2. Improvement of the tolerated raw bit-error rate in NAND Flash-based SSDs with the help of embedded statistics
    Valentin Gherman, Emna Farjallah, Jean-Marc Armani, Marcelino Seif, Luigi Dilillo
    ITC: International Test Conference, Oct 2017, Fort Worth, United States. &#x27E8;10.1109/TEST.2017.8242066&#x27E9;. &#x27E8;lirmm-01582185&#x27E9;. <10.1109/TEST.2017.8242066>
  3. Single-Event Effects in the Peripheral Circuitry of a Commercial Ferroelectric Random- Access Memory
    Alexandre Louis Bosser, Viyas Gupta, Arto Javanainen, Georgios Tsiligiannis, Stephen Lalumondiere, Dale Brewe, Véronique Ferlet-Cavrois, Helmut Puchner, Heikki Kettunen, Thierry Gil, Frédéric Wrobel, Frédéric Saigné, Ari Virtanen, Luigi Dilillo
    RADECS: Radiation and Its Effects on Components and Systems, Oct 2017, Genève, Switzerland. &#x27E8;hal-01929267&#x27E9;. <http://radecs2017.com/Radecs2017/>
  4. Towards digital circuit approximation by exploiting fault simulation
    Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
    EWDTS: East-West Design & Test Symposium, Sep 2017, Novi Sad, Serbia. &#x27E8;10.1109/EWDTS.2017.8110108&#x27E9;. &#x27E8;lirmm-01718583&#x27E9;. <10.1109/EWDTS.2017.8110108>
  5. A calculation method to estimate single event upset cross section
    Frédéric Wrobel, A. D. Touboul, V. Pouget, Luigi Dilillo, J. Boch, F. Saigné
    ESREF: European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Sep 2017, Bordeaux, France. &#x27E8;hal-01929212&#x27E9;. <https://esref2017.sciencesconf.org>
  6. Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology
    Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Galliere, Michel Renovell, Keshav Singh
    ISVLSI: International Symposium on Very Large Scale Integration, Jul 2017, Bochum, Germany. pp.320-325, &#x27E8;10.1109/ISVLSI.2017.63&#x27E9;. &#x27E8;hal-01709614&#x27E9;.
  7. Hacking the Control Flow error detection mechanism
    Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
    IVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.51-56, &#x27E8;10.1109/IVSW.2017.8031544&#x27E9;. &#x27E8;lirmm-01700739&#x27E9;.
  8. Reliability of computing systems: From flip flops to variables
    Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Regis Leveugle
    IOLTS: International On-Line Testing Symposium, Jul 2017, Thessaloniki, Greece. pp.196-198, &#x27E8;10.1109/IOLTS.2017.8046242&#x27E9;. &#x27E8;lirmm-01700744&#x27E9;.
  9. Test and reliability in approximate computing
    Lorena Anghel, Mounir Benabdenbi, Alberto Bosio, Elena Ioana Vatajelu
    IMSTW: International Mixed-Signal Testing Workshop, Jul 2017, Thessaloniki, Greece. &#x27E8;10.1109/IMS3TW.2017.7995210&#x27E9;. &#x27E8;hal-01702768&#x27E9;. <10.1109/IMS3TW.2017.7995210>
  10. Experimentations on scan chain encryption with PRESENT
    Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    IVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.45-50, &#x27E8;10.1109/IVSW.2017.8031543&#x27E9;. &#x27E8;lirmm-01699258&#x27E9;.
  11. Analytical Study of On-chip Generations of Analog Sine-wave Based on Combined Digital Signals
    Stéphane David-Grignot, Achraf Lamlih, Vincent Kerzérho, Florence Azaïs, Fabien Soulier, Serge Bernard
    IMSTW: International Mixed Signals Testing Workshop, Jul 2017, Thessaloniki, Greece. &#x27E8;10.1109/IMS3TW.2017.7995205&#x27E9;. &#x27E8;lirmm-01699387&#x27E9;. <10.1109/IMS3TW.2017.7995205>
  12. Zero bit-error-rate weak PUF based on Spin-Transfer-Torque MRAM memories
    Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto
    IVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.128-133, &#x27E8;10.1109/IVSW.2017.8031552&#x27E9;. &#x27E8;hal-01591549&#x27E9;.
  13. IDEFI-FINMINA: a French educative project for the awareness, innovation and multidisciplinarity in microelectronics
    Olivier Bonnaud, Ahmad Bsiesy, Laurent Fesquet, Beatrice Pradarelli
    27th European Association for Education in Electrical and Information Engineering Annual Conference (EAEEIE 2017), Jun 2017, Grenoble, France. &#x27E8;hal-01827895&#x27E9;.
  14. Mitigating Read & Write Errors in STT-MRAM Memories under DVS
    Elena Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras
    ETS: European Test Symposium, May 2017, Limassol, Cyprus. &#x27E8;10.1109/ETS.2017.7968209&#x27E9;. &#x27E8;hal-01525720&#x27E9;. <10.1109/ETS.2017.7968209>
  15. Detection of resistive open and short defects in FDSOI under delay-based test: Optimal V<inf>DD</inf> and body biasing conditions
    Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Galliere, Michel Renovell, Keshav Singh
    cts in FDSOI under delay-based test: Optimal VDD and body biasing conditions. ETS: European Test Symposium, May 2017, Limassol, Cyprus. &#x27E8;10.1109/ETS.2017.7968208&#x27E9;. &#x27E8;hal-01709615&#x27E9;. <10.1109/ETS.2017.7968208>
  16. Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps
    Marcelino Seif, Emna Farjallah, Franck Badets, Christophe Layer, Jean-Marc Armani, Francis Joffre, Costin Anghel, Valentin Gherman, Luigi Dilillo
    ETS: European Test Symposium, May 2017, Limassol, Cyprus. pp.1-6, &#x27E8;10.1109/ETS.2017.7968233&#x27E9;. &#x27E8;lirmm-01687675&#x27E9;.
  17. Scan chain encryption for the test, diagnosis and debug of secure circuits
    Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Paolo Prinetto, Marco Restifo
    ETS: European Test Symposium, May 2017, Limassol, Cyprus. &#x27E8;10.1109/ETS.2017.7968248&#x27E9;. &#x27E8;lirmm-01699254&#x27E9;. <10.1109/ETS.2017.7968248>
  18. Do we need a holistic approach for the design of secure IoT systems?
    Mauro Contini, Giorgio Di Natale, Annelie Heuser, Thomas Poppelmann, Nele Mentens
    Computing Frontiers Conference, May 2017, Siena, Italy. &#x27E8;hal-01628683&#x27E9;. <http://www.computingfrontiers.org/2017/>
  19. Combo of innovative educational approaches to teach industrial test to undergraduate students
    Beatrice Pradarelli, Pascal Nouet, Laurent Latorre
    EDUCON: Global Engineering Education Conference, Apr 2017, Athens, Greece. pp.56-64, &#x27E8;10.1109/EDUCON.2017.7942824&#x27E9;. &#x27E8;lirmm-01768840&#x27E9;.
  20. How to throw chocolate at students: A survey of extrinsic means for increased audience attention
    Mark Cieliebak, Amani Magid, Beatrice Pradarelli
    EDUCON: Global Engineering Education Conference, Apr 2017, Athens, Greece. pp.199-203, &#x27E8;10.1109/EDUCON.2017.7942847&#x27E9;. &#x27E8;lirmm-02021539&#x27E9;.
  21. Towards approximation during test of Integrated Circuits
    Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2017, Dresden, Germany. &#x27E8;10.1109/DDECS.2017.7934574&#x27E9;. &#x27E8;lirmm-01718580&#x27E9;. <10.1109/DDECS.2017.7934574>
  22. An effective fault-injection framework for memory reliability enhancement perspectives
    Ghita Harcha, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2017, Palma de Mallorca, Spain. &#x27E8;10.1109/DTIS.2017.7930172&#x27E9;. &#x27E8;lirmm-01718579&#x27E9;. <10.1109/DTIS.2017.7930172>
  23. Memristive devices: Technology, Design Automation and Computing Frontiers
    Mario Barbareschi, Alberto Bosio, Hoang Anh Du Nguyen, Said Hamdioui, Marcello Traiola, Elena Ioana Vatajelu
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2017, Palma de Mallorca, Spain. pp.1-8, &#x27E8;10.1109/DTIS.2017.7930178&#x27E9;. &#x27E8;hal-01525719&#x27E9;.
  24. Analysis of short defects in FinFET based logic cells
    Freddy Forero, Jean-Marc Galliere, Michel Renovell, Víctor Champac
    LATS: Latin American Test Symposium, Mar 2017, Bogota, Colombia. &#x27E8;10.1109/LATW.2017.7906755&#x27E9;. &#x27E8;hal-01709620&#x27E9;. <10.1109/LATW.2017.7906755>
  25. Approximate computing: Design & test for integrated circuits
    Arnaud Virazel, Alberto Bosio, Patrick Girard, Mario Barbareschi
    LATS: Latin American Test Symposium, Mar 2017, Bogota, Colombia. &#x27E8;10.1109/LATW.2017.7906737&#x27E9;. &#x27E8;lirmm-01718600&#x27E9;. <10.1109/LATW.2017.7906737>
  26. Can we Approximate the Test of Integrated Circuits?
    Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
    WAPCO: Workshop On Approximate Computing, Jan 2017, Stockholm, Sweden. &#x27E8;lirmm-02004418&#x27E9;. <https://wapco.e-ce.uth.gr/program.html>

2016

  1. Test of Low Power Circuits: Issues and Industrial Practices
    Alberto Bosio, Patrick Girard, Arnaud Virazel
    ICECS: International Conference on Electronics, Circuits and Systems, Dec 2016, Monte Carlo, Monaco. &#x27E8;lirmm-01433330&#x27E9;. <http://icecs.isep.fr>
  2. SCHIFI: Scalable and flexible high performance FPGA-based fault injector
    Suman Sau, Maha Kooli, Giorgio Di Natale, Alberto Bosio, Amlan Chakrabarti
    DCIS: Design of Circuits and Integrated Systems, Nov 2016, Granada, Spain. &#x27E8;10.1109/DCIS.2016.7845375&#x27E9;. &#x27E8;lirmm-01700747&#x27E9;. <10.1109/DCIS.2016.7845375>
  3. Cross-layer system reliability assessment framework for hardware faults
    Alessandro Vallero, Alessandro Savino, Gianfranco Michele Maria Politano, Stefano Di Carlo, Athanasios Chatzidimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Sotiris Tselonis, Marc Riera Villanueva, Ramon Canal, Antonio Gonzalez, Maha Kooli, Alberto Bosio, Giorgio Di Natale
    ITC: International Test Conference, Nov 2016, Fort Worth, TX, United States. &#x27E8;10.1109/TEST.2016.7805863&#x27E9;. &#x27E8;lirmm-01444774&#x27E9;. <10.1109/TEST.2016.7805863>
  4. Duplication-based Concurrent Detection of Hardware Trojans in Integrated Circuits
    Manikandan Palanichamy, Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    TRUDEVICE, Nov 2016, Barcelona, Spain. &#x27E8;lirmm-01385551&#x27E9;. <https://trudevice2016.eel.upc.edu/>
  5. True random number generator based on nanomagnets
    Luca Gnoli, Matteo Bollo, Marco Vacca, Mariagrazia Graziano, Giorgio Di Natale
    NMDC: Nanotechnology Materials and Devices Conference, Oct 2016, Toulouse, France. &#x27E8;10.1109/NMDC.2016.7777089&#x27E9;. &#x27E8;lirmm-01444398&#x27E9;. <10.1109/NMDC.2016.7777089>
  6. A Case Study on the Approximate Test of Integrated Circuits
    Imran Wali, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
    AC: Approximate Computing, Oct 2016, Pittsburgh, PA, United States. &#x27E8;lirmm-01718609&#x27E9;. <http://approximate.uni-paderborn.de/pages/general-info/welcome.php>
  7. A Hybrid Power Estimation Technique to improve IP power models quality
    Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
    VLSI-SoC: Very Large Scale Integration and System-on-Chip, Sep 2016, Tallin, Estonia. &#x27E8;10.1109/VLSI-SoC.2016.7753582&#x27E9;. &#x27E8;lirmm-01689544&#x27E9;. <10.1109/VLSI-SoC.2016.7753582>
  8. Faster-than-at-speed execution of functional programs: An experimental analysis
    Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Federico Venini
    VLSI-SoC: Very Large Scale Integration and System-on-Chip, Sep 2016, Tallinn, Estonia. &#x27E8;10.1109/VLSI-SoC.2016.7753581&#x27E9;. &#x27E8;lirmm-01444403&#x27E9;. <10.1109/VLSI-SoC.2016.7753581>
  9. Design of a Radiation Tolerant System for Total Ionizing Dose Monitoring Using Floating Gate and RadFET Dosimeters
    Rudy Ferraro, Salvatore Danzeca, Matteo Brucoli, Alessandro Masi, Markus Brugger, Luigi Dilillo
    TWEPP: Topical Workshop on Electronics for Particle Physics, Sep 2016, Karlsruhe, Germany. &#x27E8;lirmm-01382578&#x27E9;. <http://indico.cern.ch/event/489996/>
  10. Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs
    Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Ernesto Sanchez, Federico Venini
    VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability, Sep 2016, Tallinn, Estonia. pp.130-151, &#x27E8;10.1007/978-3-319-67104-8_7&#x27E9;. &#x27E8;hal-01675205&#x27E9;.
  11. Mixed-level simulation tool for design optimization of electrical impedance spectroscopy systems
    Achraf Lamlih, Vincent Kerzérho, Serge Bernard, Fabien Soulier, Mariane Comte, Michel Renovell, Tristan Rouyer, Sylvain Bonhommeau
    IWIS: International Workshop on Impedance Spectroscopy, Sep 2016, Chemnitz, Germany. &#x27E8;lirmm-01457544&#x27E9;. <https://www.tu-chemnitz.de/etit/messtech/iwis/openconf/modules/request.php?module=oc_program&action=program.php>
  12. Problem-Based Learning Approach to Teach Printed Circuit Boards Test
    Béatrice Pradarelli, Pascal Nouet, Laurent Latorre
    ICL: Interactive Collaborative Learning, Sep 2016, Belfast, United Kingdom. &#x27E8;lirmm-01385626&#x27E9;. <http://www.icl-conference.org/icl2016/>
  13. Comparison of the Effects of Muon and Low-Energy Proton Irradiation on a 65 nm Low-Power SRAM
    Alexandre Louis Bosser, Viyas Gupta, Arto Javanainen, Georgios Tsiligiannis, Helmut Puchner, Frédéric Saigné, Frédéric Wrobel, Ari Virtanen, Luigi Dilillo
    RADECS: Radiation and Its Effects on Components and Systems, Sep 2016, Bremen, Germany. &#x27E8;lirmm-01337405&#x27E9;. <http://www.radecs2016.com/joomla/>
  14. Investigation on the Sensitivity of a 65nm Flash-Based FPGA for CERN Applications
    Georgios Tsiligiannis, Rudy Ferraro, Salvatore Danzeca, Alessandro Masi, Markus Brugger, Frédéric Saigné
    RADECS: Radiation and Its Effects on Components and Systems, Sep 2016, Brême, Germany. &#x27E8;10.1109/RADECS.2016.8093209&#x27E9;. &#x27E8;hal-01824789&#x27E9;. <10.1109/RADECS.2016.8093209>
  15. Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study
    Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2016, Pittsburgh, PA, United States. pp.731-736, &#x27E8;10.1109/ISVLSI.2016.42 &#x27E9;. &#x27E8;lirmm-01446917&#x27E9;.
  16. The Power Law Shape of Heavy Ions Experimental Cross Section
    Frédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Eric Lorfèvre, Frédéric Saigné
    NSREC: Nuclear and Space Radiation Effects Conference, IEEE NPSS (Nuclear & Plasma Sciences Society ), Jul 2016, Portland, United States. &#x27E8;lirmm-01298421&#x27E9;. <http://www.nsrec.com/>
  17. Impact of VT and Body-Biasing on Resistive short detection in 28nm UTBB FDSOI – LVT and RVT configurations
    Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel Renovell
    ISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, United States. pp.164-169, &#x27E8;10.1109/ISVLSI.2016.102&#x27E9;. &#x27E8;lirmm-01374292&#x27E9;.
  18. Hardware Trust through Layout Filling: a Hardware Trojan Prevention Technique
    Papa-Sidy Ba, Sophie Dupuis, Manikandan Palanichamy, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    ISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, United States. pp.254-259, &#x27E8;10.1109/ISVLSI.2016.22&#x27E9;. &#x27E8;lirmm-01346529&#x27E9;.
  19. Towards Model Driven Design of Crypto Primitives and Processes
    Alberto Carelli, Giorgio Di Natale, Pascal Trotta, Tiziana Margaria
    SAM: Sensor Array and Multichannel Signal Processing, Jul 2016, Rio de Janeiro, Brazil. pp.152-158. &#x27E8;lirmm-01444948&#x27E9;.
  20. Cache-aware reliability evaluation through LLVM-based analysis and fault injection
    Maha Kooli, Giorgio Di Natale, Alberto Bosio
    IOLTS: International On-Line Testing Symposium, Jul 2016, Sant Feliu de Guixols, Spain. pp.19-22, &#x27E8;10.1109/IOLTS.2016.7604663&#x27E9;. &#x27E8;lirmm-01444619&#x27E9;.
  21. Revisiting software-based soft error mitigation techniques via accurate error generation and propagation models
    Mojtaba Ebrahimi, Maryam Rashvand, Firas Kaddachi, Mehdi B. Tahoori, Giorgio Di Natale
    IOLTS: International On-Line Testing Symposium, Jul 2016, Sant Feliu de Guixols, Spain. pp.66-71, &#x27E8;10.1109/IOLTS.2016.7604674&#x27E9;. &#x27E8;lirmm-01444612&#x27E9;.
  22. Using Outliers to Detect Stealthy Hardware Trojan Triggering?
    Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    IVSW: International Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, France. &#x27E8;lirmm-01347119&#x27E9;.
  23. STT-MTJ-based TRNG with on-the-fly temperature/current variation compensation
    Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto
    IOLTS: International On-Line Testing Symposium, Jul 2016, Sant Feliu de Guixols, Spain. pp.179-184, &#x27E8;10.1109/IOLTS.2016.7604694&#x27E9;. &#x27E8;lirmm-01444408&#x27E9;.
  24. MTCube project: COTS memory SEE ground-test results and in-orbit error rate prediction
    Viyas Gupta, Alexandre Louis Bosser, Frédéric Wrobel, Frédéric Saigné, Laurent Dusseau, Ali Mohammadzadeh, Luigi Dilillo
    4S: Small Satellites Systems and Services Symposium, Centre national d'études spatiales (CNES); European Space Agency (ESA), May 2016, La Valletta, Malta. &#x27E8;lirmm-01298423&#x27E9;. <http://congrexprojects.com/4S2016/home>
  25. Behavior and test of open-gate defects in FinFET based cells
    Francisco Mesalles, Hector Villacorta, Michel Renovell, Víctor Champac
    ETS: European Test Symposium, May 2016, Amsterdam, Netherlands. &#x27E8;10.1109/ETS.2016.7519305&#x27E9;. &#x27E8;lirmm-01923016&#x27E9;. <10.1109/ETS.2016.7519305>
  26. A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits
    Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
    ETS: European Test Symposium, May 2016, Amsterdam, Netherlands. &#x27E8;10.1109/ETS.2016.7519296&#x27E9;. &#x27E8;hal-01444734&#x27E9;. <10.1109/ETS.2016.7519296>
  27. Per Peers Learning Education Approach to Teach Industrial Test to Undergraduate Students
    Béatrice Pradarelli, Pascal Nouet, Laurent Latorre
    EWME: European Workshop on Microelectronics Education, May 2016, Southampton, United Kingdom. &#x27E8;lirmm-01385619&#x27E9;. <http://ewme2016.ecs.soton.ac.uk>
  28. Thermal issues in test: An overview of the significant aspects and industrial practice
    Juergen Alt, Paolo Bernardi, Alberto Bosio, Ricardo Cantoro, Hans Kerkhoff, Andreas Leininger, Wolfgang Molzer, Allessandro Motta, Christian Pacha, Alberto Pagani, Alireza Rohani, Rudolf Strasser
    VTS: VLSI Test Symposium, Apr 2016, Las Vegas, NV, United States. &#x27E8;10.1109/VTS.2016.7477278&#x27E9;. &#x27E8;lirmm-01447125&#x27E9;. <10.1109/VTS.2016.7477278>
  29. Cache- and register-aware system reliability evaluation based on data lifetime analysis
    Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio
    VTS: VLSI Test Symposium, Apr 2016, Las Vegas, United States. &#x27E8;10.1109/VTS.2016.7477299&#x27E9;. &#x27E8;lirmm-01374569&#x27E9;. <10.1109/VTS.2016.7477299>
  30. Security primitives (PUF and TRNG) with STT-MRAM
    Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto
    VTS: VLSI Test Symposium, Apr 2016, Las Vegas, United States. &#x27E8;10.1109/VTS.2016.7477292&#x27E9;. &#x27E8;lirmm-01374573&#x27E9;. <10.1109/VTS.2016.7477292>
  31. A hybrid power modeling approach to enhance high-level power models
    Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. &#x27E8;10.1109/DDECS.2016.7482453&#x27E9;. &#x27E8;lirmm-01446854&#x27E9;. <10.1109/DDECS.2016.7482453>
  32. System-level reliability evaluation through cache-aware software-based fault injection
    Firas Kaddachi, Maha Kooli, Giorgio Di Natale, Alberto Bosio, Mojtaba Ebrahimi, Mehdi B. Tahoori
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. &#x27E8;10.1109/DDECS.2016.7482446&#x27E9;. &#x27E8;lirmm-01444721&#x27E9;. <10.1109/DDECS.2016.7482446>
  33. An effective approach for functional test programs compaction
    Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. &#x27E8;10.1109/DDECS.2016.7482466&#x27E9;. &#x27E8;lirmm-01457396&#x27E9;. <10.1109/DDECS.2016.7482466>
  34. SEcube™: An open-source security platform in a single SoC
    Antonio Varriale, Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto, Pascal Trotta, Tiziana Margaria
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2016, Istanbaul, Turkey. &#x27E8;10.1109/DTIS.2016.7483810&#x27E9;. &#x27E8;lirmm-01444711&#x27E9;. <10.1109/DTIS.2016.7483810>
  35. Auto-adaptive ultra-low power IC
    Alberto Bosio, Philippe Debaud, Patrick Girard, Stéphane Guilhot, Miroslav Valka, Arnaud Virazel
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2016, Istanbaul, Turkey. &#x27E8;10.1109/DTIS.2016.7483886&#x27E9;. &#x27E8;lirmm-01457361&#x27E9;. <10.1109/DTIS.2016.7483886>
  36. Industrial Test Project Oriented Education
    Béatrice Pradarelli, Pascal Nouet, Laurent Latorre
    EDUCON: Global Engineering Education Conference, Apr 2016, Abu Dhabi, United Arab Emirates. &#x27E8;lirmm-01256447&#x27E9;. <http://www.educon-conference.org/educon2016/index.php>
  37. An effective BIST architecture for power-gating mechanisms in low-power SRAMs
    Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo B. Zordan
    ISQED: International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. pp.185-191, &#x27E8;10.1109/ISQED.2016.7479198&#x27E9;. &#x27E8;lirmm-01457424&#x27E9;.
  38. Analysis of Setup & Hold Margins Inside Silicon for Advanced Technology Nodes
    Deepak Kumar Arora, Darayus Adil Patel, Nc Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, Balwant Singh, Sylvie Naudet, Arnaud Virazel, Alberto Bosio
    ISQED: International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. pp.295-300, &#x27E8;10.1109/ISQED.2016.7479217&#x27E9;. &#x27E8;lirmm-01433314&#x27E9;.
  39. Towards a Highly Reliable SRAM-based PUFs
    Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto
    DATE: Design, Automation and Test in Europe, Mar 2016, Dresden, Germany. &#x27E8;lirmm-01374279&#x27E9;. <https://www.date-conference.com/proceedings-archive/2016/>
  40. Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect
    Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel Renovell
    LATS: Latin-American Test Symposium, Mar 2016, Foz do Iguacu, Brazil. pp.129-134, &#x27E8;10.1109/LATW.2016.7483352&#x27E9;. &#x27E8;lirmm-01374300&#x27E9;.

2015

  1. An efficient hybrid power modeling approach for accurate gate-level power estimation
    Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
    ICM: International Conference on Microelectronics, Dec 2015, Casablanca, Morocco. pp.17-20, &#x27E8;10.1109/ICM.2015.7437976&#x27E9;. &#x27E8;lirmm-01354745&#x27E9;.
  2. Validation Of Single BBICS Architecture In Detecting Multiple Faults
    Raphael Andreoni Camponogara-Viera, Rodrigo Possamai Bastos, Jean-Max Dutertre, Olivier Potin, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    ATS: Asian Test Symposium, Nov 2015, Mumbai, India. &#x27E8;lirmm-01234067&#x27E9;. <https://www.ee.iitb.ac.in/ats15/>
  3. An Experimental Comparative Study of Fault-Tolerant Architectures
    Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard
    VALID: Advances in System Testing and Validation Lifecycle, Nov 2015, Barcelone, Spain. pp.1-6. &#x27E8;lirmm-01354754&#x27E9;.
  4. Exploiting the Variability of the Magnetic Tunnel Junction for Security Purposes
    Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto
    e-NVM: Leading Edge Embedded NVM, Sep 2015, Gardanne, France. &#x27E8;lirmm-01276293&#x27E9;.
  5. SEcubeTM: The most advanced, Open Source Security Platform in a Single Chip
    Antonio Varriale, Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto, Tiziana Margaria
    TRUDEVICE Workshop, Sep 2015, Saint-Malo, France. &#x27E8;lirmm-01276298&#x27E9;.
  6. Zero Bit-Error-Rate Weak PUF based on Spin-Transfer-Torque MRAM Memories
    Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto
    TRUDEVICE Workshop, Sep 2015, Saint-Malo, France. &#x27E8;lirmm-01276300&#x27E9;.
  7. Multi-segment Enhanced Scan-chains for Secure ICs
    Mafalda Cortez, Said Hamdioui, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ilia Polian
    TRUDEVICE Workshop, Sep 2015, Saint-Malo, France. &#x27E8;lirmm-01276304&#x27E9;.
  8. Sensitivity to fault laser injection: a comparison between 28nm bulk and FD-SOI technology
    Stephan de Castro, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    TRUDEVICE Workshop, Sep 2015, Saint-Malo, France. &#x27E8;lirmm-01234094&#x27E9;.
  9. Hierarchical Secure DfT
    Mafalda Cortez, Said Hamdioui, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    TRUDEVICE Workshop, Sep 2015, St Malo, France. &#x27E8;lirmm-01234095&#x27E9;.
  10. Proton-Induced SDRAM Cell Degradation
    Axel Rodriguez, Frédéric Wrobel, Anne Samaras, Francoise Bezerra, Benjamin Vandevelde, Robert Ecoffet, Antoine Touboul, Nathalie Chatry, Luigi Dilillo, Frédéric Saigné
    RADECS: Radiation and Its Effects on Components and Systems, Sep 2015, Moscou, Russia. &#x27E8;10.1109/RADECS.2015.7365650&#x27E9;. &#x27E8;lirmm-01238408&#x27E9;. <10.1109/RADECS.2015.7365650>
  11. A Methodology for the Analysis of Memory Response to Radiation through Bitmap Superposition and Slicing
    Alexandre Louis Bosser, Viyas Gupta, Georgios Tsiligiannis, Rudy Ferraro, Christopher Frost, Ali Mohammadzadeh, Arto Javanainen, Helmut Puchner, Mario Rossi, Frédéric Saigné, Ari Virtanen, Frédéric Wrobel, Luigi Dilillo
    RADECS: Radiation and Its Effects on Components and Systems, Sep 2015, Moscou, Russia. &#x27E8;10.1109/RADECS.2015.7365578&#x27E9;. &#x27E8;lirmm-01238397&#x27E9;. <10.1109/RADECS.2015.7365578>
  12. Heavy-ion radiation impact on a 4Mb FRAM under Different Test Conditions
    Viyas Gupta, Alexandre Louis Bosser, Georgios Tsiligiannis, Ali Mohammadzadeh, Arto Javanainen, Ari Virtanen, Helmut Puchner, Frédéric Saigné, Frédéric Wrobel, Luigi Dilillo
    RADECS: Radiation and Its Effects on Components and Systems, Sep 2015, Moscou, Russia. &#x27E8;10.1109/RADECS.2015.7365617&#x27E9;. &#x27E8;lirmm-01238392&#x27E9;. <10.1109/RADECS.2015.7365617>
  13. Hardware Trojan Prevention using Layout-Level Design Approach
    Papa-Sidy Ba, Manikandan Palanichamy, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    ECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. &#x27E8;10.1109/ECCTD.2015.7300093&#x27E9;. &#x27E8;lirmm-01234072&#x27E9;. <10.1109/ECCTD.2015.7300093>
  14. Generic Analytic Expression of Heavy Ion SEU Cross Section Derived from Monte-Carlo Diffusion-Based Prediction Code
    Frédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Robert Ecoffet, Eric Lorfèvre, Francoise Bezerra, Markus Brugger, Ruben Garcia Alia, Frédéric Saigné
    NSREC: Nuclear and Space Radiation Effects Conference, IEEE / NPSS, Jul 2015, Boston, United States. &#x27E8;lirmm-01238388&#x27E9;. <http://www.nsrec.com/2015Brochure.pdf>
  15. Investigation on MCU Clustering Methodologies for Cross-Section Estimation of RAMs
    Alexandre Louis Bosser, Viyas Gupta, Georgios Tsiligiannis, Arto Javanainen, Heikki Kettunen, Helmut Puchner, F. Saigné, Ari Virtanen, Frédéric Wrobel, Luigi Dilillo
    NSREC: Nuclear and Space Radiation Effects Conference, Jul 2015, Boston, MA, United States. &#x27E8;hal-01932433&#x27E9;.
  16. Impact of Stacked-Layer Structure on SEE Rate of SRAMs
    Viyas Gupta, Alexandre Louis Bosser, Georgios Tsiligiannis, Ali Mohammadzadeh, Arto Javanainen, Ari Virtanen, Helmut Puchner, Frédéric Saigné, Frédéric Wrobel, Luigi Dilillo
    NSREC: Nuclear and Space Radiation Effects Conference, IEEE / NPSS, Jul 2015, Boston, United States. &#x27E8;lirmm-01238384&#x27E9;.
  17. An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern
    Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.515-520, &#x27E8;10.1109/ISVLSI.2015.99&#x27E9;. &#x27E8;lirmm-01272933&#x27E9;.
  18. 3D DFT Challenges and Solutions
    Yassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Juergen Schloeffel
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.603-608, &#x27E8;10.1109/ISVLSI.2015.11&#x27E9;. &#x27E8;lirmm-01234076&#x27E9;.
  19. Figure of merits of 28nm Si technologies for implementing laser attack resistant security dedicated circuits
    Stephan de Castro, Jean-Max Dutertre, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.362-367, &#x27E8;10.1109/ISVLSI.2015.76&#x27E9;. &#x27E8;emse-01227138&#x27E9;.
  20. Digital Right Management for IP Protection
    Jerome Rampon, Renaud Perillat, Lionel Torres, Pascal Benoit, Giorgio Di Natale, Mario Barbareschi
    ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.200-203, &#x27E8;10.1109/ISVLSI.2015.127&#x27E9;. &#x27E8;lirmm-01234082&#x27E9;.
  21. A framework for efficient implementation of analog/RF alternate test with model redundancy
    Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, Michel Renovell
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.621-626, &#x27E8;10.1109/ISVLSI.2015.30&#x27E9;. &#x27E8;lirmm-01233104&#x27E9;.
  22. Toward adaptation of ADCs to operating conditions through on-chip correction
    Vincent Kerzérho, Ludovic Guillaume-Sage, Florence Azaïs, Mariane Comte, Michel Renovell, Serge Bernard
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.634-639, &#x27E8;10.1109/ISVLSI.2015.62&#x27E9;. &#x27E8;lirmm-01233117&#x27E9;.
  23. STT-MRAM-Based Strong PUF Architecture
    Ioana Vatajelu, Giorgio Di Natale, Lionel Torres, Paolo Prinetto
    ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.467-472, &#x27E8;10.1109/ISVLSI.2015.128&#x27E9;. &#x27E8;lirmm-01234079&#x27E9;.
  24. Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture
    Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
    IOLTS: International On-Line Testing Symposium, Jul 2015, Halkidiki, Greece. pp.89-94, &#x27E8;10.1109/IOLTS.2015.7229838&#x27E9;. &#x27E8;lirmm-01272735&#x27E9;.
  25. Digital on-chip measurement circuit for built-in phase noise testing
    Stéphane David-Grignot, Florence Azaïs, Laurent Latorre, François Lefevre
    IMSTW: International Mixed-Signals Test Workshop, Jun 2015, Paris, France. &#x27E8;10.1109/IMS3TW.2015.7177880&#x27E9;. &#x27E8;lirmm-01233161&#x27E9;. <10.1109/IMS3TW.2015.7177880>
  26. A generic methodology for building efficient prediction models in the context of alternate testing
    Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, Michel Renovell
    IMSTW: International Mixed-Signals Test Workshop, Jun 2015, Paris, France. &#x27E8;10.1109/IMS3TW.2015.7177873&#x27E9;. &#x27E8;lirmm-01233150&#x27E9;. <10.1109/IMS3TW.2015.7177873>
  27. Real-Time SRAM Based Particle Detector
    Luigi Dilillo, Alexandre Louis Bosser, Viyas Gupta, Frédéric Wrobel, Frédéric Saigné
    IWASI: International Workshop on Advances in Sensors and Interfaces, IEEE; Politecnico di Bari, Jun 2015, Gallipoli, Italy. pp.58-62, &#x27E8;10.1109/IWASI.2015.7184968&#x27E9;. &#x27E8;lirmm-01238435&#x27E9;.
  28. Une pedagogie par projet pour des etudiants acteurs et auteurs de leur apprentissage
    Béatrice Pradarelli, Pascal Nouet, Laurent Latorre
    QPES: Questions de Pédagogie dans l’Enseignement Supérieur, Jun 2015, Brest, France. &#x27E8;lirmm-01256445&#x27E9;. <http://www.colloque-pedagogie.org/?q=node/5>
  29. Power-aware voltage tuning for STT-MRAM reliability
    Elena Ioana Vatajelu, Rosa Rodríguez-Montañés, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras
    ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. &#x27E8;10.1109/ETS.2015.7138748&#x27E9;. &#x27E8;lirmm-01922971&#x27E9;. <10.1109/ETS.2015.7138748>
  30. Analog test: Why still “à la mode” after more than 25 years of research?
    Florence Azaïs
    ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. &#x27E8;10.1109/ETS.2015.7138772&#x27E9;. &#x27E8;lirmm-01922917&#x27E9;. <10.1109/ETS.2015.7138772>
  31. An effective hybrid fault-tolerant architecture for pipelined cores
    Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard
    ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. pp.1-6, &#x27E8;10.1109/ETS.2015.7138733&#x27E9;. &#x27E8;lirmm-01272730&#x27E9;.
  32. Session-less based thermal-aware 3D-SIC test scheduling
    Marie-Lise Flottes, João Azevedo, Giorgio Di Natale, Bruno Rouzeyre
    ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. &#x27E8;10.1109/ETS.2015.7138732&#x27E9;. &#x27E8;lirmm-01922990&#x27E9;. <10.1109/ETS.2015.7138732>
  33. A New Technique for Low-Cost Phase Noise Production Testing from 1-bit Signal Acquisition
    Stéphane David-Grignot, Florence Azaïs, Laurent Latorre, François Lefevre
    ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. pp.1-6, &#x27E8;10.1109/ETS.2015.7138761&#x27E9;. &#x27E8;lirmm-01233093&#x27E9;.
  34. Challenges in Designing Trustworthy Cryptographic Co-Processors
    Ricardo Chaves, Giorgio Di Natale, Lejla Batina, Shivam Bhasin, Baris Ege, Apostolos Fournaris, Nele Mentens, Stjepan Picek, Francesco Regazzoni, Vladimir Rozic, Nicolas Sklavos, Bohan Yang
    ISCAS: International Symposium on Circuits and Systems, May 2015, Lisbon, Portugal. pp.2009-2010, &#x27E8;10.1109/ISCAS.2015.7169070&#x27E9;. &#x27E8;lirmm-01234083&#x27E9;.
  35. Special session: Hot topics: Statistical test methods
    Manuel J. Barragan, Gildas Leger, Florence Azaïs, R. D. Blanton, Adit D. Singh, Stephen Sunter
    VTS: VLSI Test Symposium, Apr 2015, Napa, CA, United States. &#x27E8;10.1109/VTS.2015.7116265&#x27E9;. &#x27E8;hal-01177043&#x27E9;. <10.1109/VTS.2015.7116265>
  36. Design-for-Diagnosis Architecture for Power Switches
    Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Philippe Debaud, Stephane Guilhot
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2015, Belgrade, Serbia. pp.43-48, &#x27E8;10.1109/DDECS.2015.18&#x27E9;. &#x27E8;lirmm-01272684&#x27E9;.
  37. Embedded test instrument for on-chip phase noise evaluation of analog/IF signals
    Florence Azaïs, Stéphane David-Grignot, Laurent Latorre, François Lefevre
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2015, Belgrade, Serbia. pp.237-242, &#x27E8;10.1109/DDECS.2015.11&#x27E9;. &#x27E8;lirmm-01233136&#x27E9;.
  38. Scan-chain intra-cell defects grading
    Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. pp.1-6, &#x27E8;10.1109/DTIS.2015.7127349&#x27E9;. &#x27E8;lirmm-01272696&#x27E9;.
  39. On the limitations of logic testing for detecting Hardware Trojans Horses
    Marie-Lise Flottes, Sophie Dupuis, Papa-Sidy Ba, Bruno Rouzeyre
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. &#x27E8;10.1109/DTIS.2015.7127362&#x27E9;. &#x27E8;lirmm-01257837&#x27E9;. <10.1109/DTIS.2015.7127362>
  40. An effective ATPG flow for Gate Delay Faults
    Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. pp.1-6, &#x27E8;10.1109/DTIS.2015.7127350&#x27E9;. &#x27E8;lirmm-01272719&#x27E9;.
  41. Software testing and software fault injection
    Maha Kooli, Alberto Bosio, Pascal Benoit, Lionel Torres
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. &#x27E8;10.1109/DTIS.2015.7127370&#x27E9;. &#x27E8;lirmm-01297579&#x27E9;. <10.1109/DTIS.2015.7127370>
  42. Statistical Energy Study for 28nm FDSOI Devices
    Rida Kheirallah, Jean-Marc Galliere, Aida Todri-Sanial, Gilles Ducharme, Nadine Azemard
    EuroSimE: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, Apr 2015, Budapest, Hungary. &#x27E8;10.1109/EuroSimE.2015.7103149&#x27E9;. &#x27E8;lirmm-01168602&#x27E9;. <10.1109/EuroSimE.2015.7103149>
  43. Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology
    Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard
    ISQED: International Symposium on Quality Electronic Design, Apr 2015, Santa Clara, United States. pp.366-370, &#x27E8;10.1109/ISQED.2015.7085453&#x27E9;. &#x27E8;lirmm-01272913&#x27E9;.
  44. A digital technique for the evaluation of SSB phase noise of analog/RF signals
    Florence Azaïs, Stéphane David-Grignot, François Lefevre, Laurent Latorre
    LATS: Latin-American Test Symposium, Mar 2015, Puerto Vallarta, Mexico. &#x27E8;10.1109/LATW.2015.7102407&#x27E9;. &#x27E8;lirmm-01233125&#x27E9;. <10.1109/LATW.2015.7102407>
  45. Ring Oscillators Analysis for FPGA Security Purposes
    Mario Barbareschi, Giorgio Di Natale, Florent Bruguier, Pascal Benoit, Lionel Torres
    TRUDEVICE, Mar 2015, Grenoble, France. &#x27E8;lirmm-01419909&#x27E9;.
  46. Exploring the impact of functional test programs re-used for power-aware testing
    Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
    DATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. pp.1277-1280. &#x27E8;lirmm-01272937&#x27E9;.
  47. New Testing Procedure for Finding Insertion Sites of Stealthy Hardware Trojans
    Sophie Dupuis, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Papa-Sidy Ba
    DATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. &#x27E8;lirmm-01141619&#x27E9;.
  48. STT MRAM-Based PUFs
    Ioana Vatajelu, Giorgio Di Natale, Marco Indaco, Paolo Prinetto
    DATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. pp.872-875. &#x27E8;lirmm-01234087&#x27E9;.

2014

  1. On the Generation of Diagnostic Test Set for Intra-cell Defects
    Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Etienne Auvray
    ATS: Asian Test Symposium, Nov 2014, Hangzhou, China. pp.312-317, &#x27E8;10.1109/ATS.2014.57&#x27E9;. &#x27E8;lirmm-01272539&#x27E9;.
  2. Low-cost phase noise testing of complex RF ICs using standard digital ATE
    Stéphane David-Grignot, Florence Azaïs, Laurent Latorre, François Lefevre
    ITC: International Test Conference, Oct 2014, Seattle, WA, United States. &#x27E8;10.1109/TEST.2014.7035301&#x27E9;. &#x27E8;lirmm-01119356&#x27E9;. <10.1109/TEST.2014.7035301>
  3. TRUDEVICE Project: Trustworthy Manufacturing and Utilization of Secure Devices
    Nicolas Sklavos, Giorgio Di Natale
    HiPEAC Computing Systems Week (CSW), Oct 2014, Athens, Greece. &#x27E8;lirmm-01234099&#x27E9;. <https://www.hipeac.net/csw/2014/athens/>
  4. Laser-Induced Fault Effects in Security-Dedicated Circuits
    Vincent Beroulle, Philippe Candelier, Stephan de Castro, Giorgio Di Natale, Jean-Max Dutertre, Marie-Lise Flottes, David Hely, Guillaume Hubert, Régis Leveugle, Feng Lu, Paolo Maistri, Athanasios Papadimitriou, Bruno Rouzeyre, Clement Tavernier, Pierre Vanhauwaert
    VLSI-SoC: Very Large Scale Integration and System-on-Chip, Oct 2014, Playa del Carmen, Mexico. pp.220-240, &#x27E8;10.1007/978-3-319-25279-7_12&#x27E9;. &#x27E8;hal-01383737&#x27E9;.
  5. Secure Test Method for Fuzzy Extractor
    Mafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di Natale
    Joint MEDIAN-TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands. &#x27E8;lirmm-01234106&#x27E9;.
  6. Multi-stage Cross-layer Hardware Trojan Prevention, Detection and Tolerance
    Cristiana Bolchini, Luca Cassano, Giorgio Di Natale
    Joint MEDIAN-TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands. &#x27E8;lirmm-01234110&#x27E9;.
  7. MRAM-based PUF
    Giorgio Di Natale, Paolo Prinetto, Ioana Vatajelu
    Joint MEDIAN-TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands. &#x27E8;lirmm-01234112&#x27E9;.
  8. Study of adaptive tuning strategies for Near Field Communication (NFC) transmitter module
    Mouhamadou Dieng, Florence Azaïs, Mariane Comte, Serge Bernard, Vincent Kerzérho, Michel Renovell, Thibault Kervaon, Paul-Henri Pugliesi-Conti
    IMS3TW'14: International Mixed-Signals, Sensors, and Systems Test Workshop, Sep 2014, Porto ALegre, Brazil. pp.1-6, &#x27E8;10.1109/IMS3TW.2014.6997401&#x27E9;. &#x27E8;lirmm-01119365&#x27E9;.
  9. Stochastic model for phase noise measurement from 1-bit signal acquisition
    Stéphane David-Grignot, Florence Azaïs, François Lefevre, Laurent Latorre
    IMS3TW'14: International Mixed-Signals, Sensors, and Systems Test Workshop, Sep 2014, Porto Alegre, Brazil. pp.1-6, &#x27E8;10.1109/IMS3TW.2014.6997400&#x27E9;. &#x27E8;lirmm-01119368&#x27E9;.
  10. Cross-Layer Early Reliability Evaluation for the Computing Continuum
    Stefano Di Carlo, Alessandro Vallero, Dirnitris Gizopoulos, Giorgio Di Natale
    DSD: Digital System Design, Aug 2014, Verona, Italy. pp.199-205, &#x27E8;10.1109/DSD.2014.65&#x27E9;. &#x27E8;lirmm-01234117&#x27E9;.
  11. Single Event Upset Prediction from Heavy Ions Cross Sections with No Parameters
    Frédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Frédéric Saigné
    NSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France. &#x27E8;lirmm-01237668&#x27E9;. <http://ieee-npss.org/wp-content/uploads/2014/03/2014-NSREC.pdf>
  12. Use of CCD to Detect Terrestrial Cosmic Rays at Ground Level: Altitude Vs. Underground Experiments, Modeling and Numerical Monte Carlo Simulation
    Tarek Saad Saoud, Soilihi Moindjie, Jean-Luc Autran, Daniela Munteanu, Frédéric Wrobel, Frédéric Saigné, Philippe Cocquerez, Luigi Dilillo
    NSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France. &#x27E8;lirmm-01237717&#x27E9;. <http://ieee-npss.org/wp-content/uploads/2014/03/2014-NSREC.pdf>
  13. SEU Cross Section Calculation Based on Experimental Data of Another kind of Particle
    A. D. Touboul, Frédéric Wrobel, V. Pouget, Luigi Dilillo, Frédéric Saigné, Robert Ecoffet, Eric Lorfèvre, Francoise Bezerra, Markus Brugger
    NSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France. &#x27E8;hal-01934616&#x27E9;. <http://ieee-npss.org/wp-content/uploads/2014/03/2014-NSREC.pdf>
  14. Real-Time Testing of 90nm COTS SRAMs at Concordia Station in Antarctica
    Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Philippe Cocquerez, Jean-Luc Autran, Antonio Litterio, Frédéric Wrobel, Frédéric Saigné
    NSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France. &#x27E8;lirmm-01237709&#x27E9;. <http://ieee-npss.org/wp-content/uploads/2014/03/2014-NSREC.pdf>
  15. Efficient Dynamic Test Methods for COTS SRAMs Under Heavy Ion Irradiation
    Georgios Tsiligiannis, Luigi Dilillo, Viyas Gupta, Alberto Bosio, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Helmut Puchner, Alexandre Louis Bosser, Arto Javanainen, Ari Virtanen, Frédéric Wrobel, Laurent Dusseau, Frédéric Saigné
    NSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France. &#x27E8;lirmm-01237660&#x27E9;.
  16. 2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures
    Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Juergen Schloeffel
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2014, Tampa, Florida, United States. pp.386-391, &#x27E8;10.1109/ISVLSI.2014.83&#x27E9;. &#x27E8;lirmm-01119605&#x27E9;.
  17. A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise
    Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2014, Tampa, FL, United States. pp.226-231, &#x27E8;10.1109/ISVLSI.2014.42&#x27E9;. &#x27E8;lirmm-01248592&#x27E9;.
  18. Customized Cell Detector for Laser-Induced-Fault Detection
    Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    IOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Spain. pp.37-42, &#x27E8;10.1109/IOLTS.2014.6873669&#x27E9;. &#x27E8;lirmm-01119576&#x27E9;.
  19. A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware Trojans
    Sophie Dupuis, Papa-Sidy Ba, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    IOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Girona, Spain. pp.49-54, &#x27E8;10.1109/IOLTS.2014.6873671&#x27E9;. &#x27E8;lirmm-01025275&#x27E9;.
  20. Cross-Layer Early Reliability Evaluation: Challenges and Promises
    Stefano Di Carlo, Alessandro Vallero, Dimitris Gizopoulos, Giorgio Di Natale, Antonio Gonzales, Ramon Canal, Riccardo Mariani, Mauro Pipponzi, Arnaud Grasset, Philippe Bonnot, Frank Reichenback, Gulzaib Rafiw, Trond Loekstad
    IOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Girona, Spain. pp.228-233, &#x27E8;10.1109/IOLTS.2014.6873704&#x27E9;. &#x27E8;lirmm-01234123&#x27E9;.
  21. Self-Adaptive NFC Systems
    Vincent Kerzérho, Florence Azaïs, Mouhamadou Dieng, Mariane Comte, Serge Bernard, Michel Renovell, Paul-Henri Pugliesi-Conti, Thibault Kervaon
    IOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Spain. &#x27E8;lirmm-01084355&#x27E9;.
  22. Solutions for the self-adaptation of communicating systems in operation
    Martin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azaïs, Serge Bernard, Philippe Cauvet, Mariane Comte, Thibault Kervaon, Vincent Kerzérho, Salvador Mir, Paul-Henri Pugliesi-Conti, Michel Renovell, Fabien Soulier, Emmanuel Simeu, Haralampos-G Stratigopoulos
    IOLTS: International On-line Test Symposium, Jul 2014, Platja d’Aro, Spain. pp.234-239, &#x27E8;10.1109/IOLTS.2014.6873705&#x27E9;. &#x27E8;hal-01118068&#x27E9;.
  23. Phase noise measurement on IF analog signals using standard digital ATE resources
    Stéphane David-Grignot, Laurent Latorre, Florence Azaïs, François Lefevre
    NEWCAS: New Circuits and Systems, Jun 2014, Trois-Rivieres, Canada. pp.121-124, &#x27E8;10.1109/NEWCAS.2014.6933998&#x27E9;. &#x27E8;lirmm-01119359&#x27E9;.
  24. Simulating Laser Effects on ICs, from Physical Level to Gate Level: a comprehensive approach
    Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    TRUDEVICE Workshop, May 2014, Paderborn, Germany. &#x27E8;lirmm-01119614&#x27E9;. <http://www.ets14.de/media/PDFs/workshops/TRUDEVICE-ETS14-PreliminaryProgam>
  25. Investigations on alternate analog/RF test with model redundancy
    Haithem Ayari, Florence Azaïs, Serge Bernard, Vincent Kerzérho, Syhem Larguech, Mariane Comte, Michel Renovell
    STEM Workshop, May 2014, Paderborn, Germany. &#x27E8;lirmm-01119374&#x27E9;. <http://www.ets14.de/pages/workshops/stem-workshop.php>
  26. A novel Adaptive Fault Tolerant Flip-Flop Architecture based on TMR
    Luca Cassano, Alberto Bosio, Giorgio Di Natale
    ETS: European Test Symposium, May 2014, Paderborn, Germany. &#x27E8;10.1109/ETS.2014.6847831&#x27E9;. &#x27E8;lirmm-01234133&#x27E9;. <10.1109/ETS.2014.6847831>
  27. iBoX — Jitter based Power Supply Noise sensor
    Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri-Sanial, Arnaud Virazel, Patrick Girard, Philippe Debaud, Stephane Guilhot
    ETS: European Test Symposium, May 2014, Paderborn, United States. pp.1-2, &#x27E8;10.1109/ETS.2014.6847830&#x27E9;. &#x27E8;lirmm-01248601&#x27E9;.
  28. Presentation of the MTCube CubeSat Project
    Viyas Gupta, Luigi Dilillo, Frédéric Wrobel, Ali Mohammadzadeh, Georgios Tsiligiannis, Muriel Bernard, Laurent Dusseau
    4S: Small Satellites Systems and Services Symposium, European Space Agency (ESA); Centre National d'Etudes Spatiales (CNES), May 2014, Majorca, Spain. &#x27E8;lirmm-01272951&#x27E9;. <http://congrexprojects.com/2014-events/4S2014/home>
  29. Fault injection tools based on Virtual Machines
    Maha Kooli, Giorgio Di Natale, Pascal Benoit, Alberto Bosio, Lionel Torres, Volkmar Sieh
    ReCoSoC: Reconfigurable and Communication-Centric Systems-on-Chip, May 2014, Montpellier, France. &#x27E8;10.1109/ReCoSoC.2014.6861351&#x27E9;. &#x27E8;hal-01075479&#x27E9;. <10.1109/ReCoSoC.2014.6861351>
  30. Radiation Study of a 4Mbit Ferroelectric RAM for Space Applications
    Helmut Puchner, Georgios Tsiligiannis, Luigi Dilillo
    SEE: Single Event Effects, Aeroflex Corporation, the Aerospace Corporation, Brigham Young University, Lockheed Martin, the NASA Electronic Parts and Packaging Program, the Naval Research Laboratory, Sandia National Laboratories, and Vanderbilt University, May 2014, San Diego, United States. &#x27E8;lirmm-01297441&#x27E9;. <http://radhome.gsfc.nasa.gov/radhome/see_mapld/2014/index.cfm>
  31. A Comprehensive Evaluation of Functional Programs for Power-Aware Test
    Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Paolo Bernardi
    NATW: North Atlantic Test Workshop, May 2014, Johnson City, NY, United States. pp.69-72, &#x27E8;10.1109/NATW.2014.23&#x27E9;. &#x27E8;lirmm-01248597&#x27E9;.
  32. Layout-Aware Laser Fault Injection Simulation and Modeling: from physical level to gate level
    Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. &#x27E8;10.1109/DTIS.2014.6850665&#x27E9;. &#x27E8;lirmm-01119592&#x27E9;. <10.1109/DTIS.2014.6850665>
  33. Laser attacks on integrated circuits: from CMOS to FD-SOI
    Jean-Max Dutertre, Stephan de Castro, Alexandre Sarafianos, Noémie Boher, Bruno Rouzeyre, Mathieu Lisart, Joel Damiens, Philippe Candelier, Marie-Lise Flottes, Giorgio Di Natale
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. &#x27E8;10.1109/DTIS.2014.6850664&#x27E9;. &#x27E8;emse-01099042&#x27E9;. <10.1109/DTIS.2014.6850664>
  34. A survey on simulation-based fault injection tools for complex systems
    Maha Kooli, Giorgio Di Natale
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorini, Greece. &#x27E8;10.1109/DTIS.2014.6850649&#x27E9;. &#x27E8;hal-01075473&#x27E9;. <10.1109/DTIS.2014.6850649>
  35. Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce
    Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.207-212, &#x27E8;10.1109/DDECS.2014.6868791&#x27E9;. &#x27E8;lirmm-01248599&#x27E9;.
  36. Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults
    Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.223-225, &#x27E8;10.1109/DDECS.2014.6868794&#x27E9;. &#x27E8;lirmm-01248598&#x27E9;.
  37. Test and diagnosis of power switches
    Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri-Sanial, Arnaud Virazel, Patrick Girard, Philippe Debaud, Stephane Guilhot
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.213-218, &#x27E8;10.1109/DDECS.2014.6868792&#x27E9;. &#x27E8;lirmm-01248590&#x27E9;.
  38. Timing-aware ATPG for critical paths with multiple TSVs
    Carolina Momo Metzeler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.116-121, &#x27E8;10.1109/DDECS.2014.6868774&#x27E9;. &#x27E8;lirmm-01248600&#x27E9;.
  39. An intra-cell defect grading tool
    Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Stefano Bernabovi, Paolo Bernardi
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.298-301, &#x27E8;10.1109/DDECS.2014.6868814&#x27E9;. &#x27E8;lirmm-01248591&#x27E9;.
  40. Built-In Self-Test for Manufacturing TSV Defects before bonding
    Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche
    VTS: VLSI Test Symposium, Apr 2014, Napa, CA, United States. pp.1-6, &#x27E8;10.1109/VTS.2014.6818771&#x27E9;. &#x27E8;lirmm-00989682&#x27E9;.
  41. TSV aware timing analysis and diagnosis in paths with multiple TSVs
    Carolina Momo Metzeler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Apr 2014, Napa, CA, United States. &#x27E8;10.1109/VTS.2014.6818772&#x27E9;. &#x27E8;lirmm-01248594&#x27E9;. <10.1109/VTS.2014.6818772>
  42. Testing PUF-Based Secure Key Storage Circuits
    Mafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di Natale
    DATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. pp.1-6, &#x27E8;10.7873/DATE.2014.207&#x27E9;. &#x27E8;lirmm-01234141&#x27E9;.
  43. Hacking and Protecting IC Hardware
    Said Hamdioui, Giorgio Di Natale, Battum Van, Jean-Luc Danger, Fethulah Smailbegovic, Mark Tehranipoor
    DATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. pp.1-7, &#x27E8;10.7873/DATE.2014.112&#x27E9;. &#x27E8;lirmm-01234147&#x27E9;.
  44. New implementions of predictive alternate analog/RF test with augmented model redundancy
    Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, Michel Renovell
    DATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. &#x27E8;10.7873/DATE2014.144&#x27E9;. &#x27E8;lirmm-00994714&#x27E9;. <10.7873/DATE2014.144>
  45. Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing
    Syhem Larguech, Florence Azaïs, Serge Bernard, Vincent Kerzérho, Mariane Comte, Michel Renovell
    LATW: Latin American Test Workshop, Mar 2014, Fortaleza, Brazil. pp.1-6, &#x27E8;10.1109/LATW.2014.6841930&#x27E9;. &#x27E8;lirmm-01119361&#x27E9;.
  46. Experimental Heavy-Ion SEU Cross-Sections Of Sram Memory Components
    Alexandre Louis Bosser, Luigi Dilillo, Viyas Gupta, Arto Javanainen, Heikki Kettunen, Mario Rossi, Georgios Tsiligiannis, Ari Virtanen
    Physics Days: Annual Meeting of the Finnish Physical Society, Finnish Physical Society, Tampere University of Technology (TUT), and Tavicon Ltd., Mar 2014, Tampere, Finland. &#x27E8;lirmm-01238439&#x27E9;. <http://webhotel2.tut.fi/fys/physicsdays/>
  47. Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration
    Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
    ASP-DAC: Asia and South Pacific Design Automation Conference, Jan 2014, Singapore, Singapore. pp.544-549, &#x27E8;10.1109/ASPDAC.2014.6742948&#x27E9;. &#x27E8;lirmm-01248596&#x27E9;.

Mots-clés

Fiabilité, Circuits et Systèmes Intégrés, Numérique, Analogique, RF, Circuits Sécurisés, Confiance matérielle, Sécurité matérielle, Technologies émergentes, Environnement spatial et radiatif, Méthodologies et Outils de Conception, Génération de tests, Simulation de fautes, Diagnostic de pannes, Attaques du matériel, Contre-mesures, Test, Modélisation

Dernière mise à jour le 22/01/2019